High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip / / by Zheng Wang, Anupam Chattopadhyay

• Autore: Wang Zheng
• Pubblicazione: Singapore : , : Springer Singapore : , : Imprint : Springer, , 2018
• Edizione: 1st ed. 2018.
• Descrizione fisica: 1 online resource (XX, 197 p. 104 illus., 72 illus. in color.)
• Disciplina: 621.3815
• Soggetto topico: Electronic circuits; Computer software—Reusability; Circuits and Systems; Performance and Reliability; Electronic Circuits and Devices
• Persona (resp. second.): ChattopadhyayAnupam
• Nota di bibliografia: Includes bibliographical references.
• Nota di contenuto: Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.
• Sommario/riassunto: This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
• Titolo autorizzato: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
• ISBN: 981-10-1073-0
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 9910299571203321
• Lo trovi qui: Univ. Federico II
• Serie: Computer Architecture and Design Methodologies, . 2367-3478