LEADER 00920nam0-2200313---450- 001 990009642290403321 005 20121205120633.0 010 $a978-88-238-3338-8 035 $a000964229 035 $aFED01000964229 035 $a(Aleph)000964229FED01 035 $a000964229 100 $a20121105d2012----km-y0itay50------ba 101 0 $aita 105 $ay-------001yy 200 1 $a<>analisi del bilancio delle banche$erischi, misure di performance, adeguatezza patrimoniale$fa cura di Michele Rutigliano 210 $aMilano$cEgea$d2012 215 $aXXIV, 558 p.$d24 cm 225 1 $aReference 676 $a658.15 702 1$aRutigliano,$bMichele 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990009642290403321 952 $aAZRAG135A$b20878$fDECBC 952 $aAZRAG135B$b20932$fDECBC 959 $aDECBC 996 $aAnalisi del bilancio delle banche$964964 997 $aUNINA LEADER 02715nam 22005415 450 001 9910299571203321 005 20250505000108.0 010 $a981-10-1073-0 024 7 $a10.1007/978-981-10-1073-6 035 $a(CKB)3710000001411805 035 $a(DE-He213)978-981-10-1073-6 035 $a(MiAaPQ)EBC4884375 035 $a(PPN)20298902X 035 $a(EXLCZ)993710000001411805 100 $a20170623d2018 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aHigh-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip /$fby Zheng Wang, Anupam Chattopadhyay 205 $a1st ed. 2018. 210 1$aSingapore :$cSpringer Nature Singapore :$cImprint: Springer,$d2018. 215 $a1 online resource (XX, 197 p. 104 illus., 72 illus. in color.) 225 1 $aComputer Architecture and Design Methodologies,$x2367-3486 311 08$a981-10-1072-2 320 $aIncludes bibliographical references. 327 $aIntroduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook. 330 $aThis book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . 410 0$aComputer Architecture and Design Methodologies,$x2367-3486 606 $aElectronic circuits 606 $aComputers 606 $aElectronic Circuits and Systems 606 $aHardware Performance and Reliability 615 0$aElectronic circuits. 615 0$aComputers. 615 14$aElectronic Circuits and Systems. 615 24$aHardware Performance and Reliability. 676 $a621.3815 700 $aWang$b Zheng$4aut$4http://id.loc.gov/vocabulary/relators/aut$0514725 702 $aChattopadhyay$b Anupam$4aut$4http://id.loc.gov/vocabulary/relators/aut 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910299571203321 996 $aHigh-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip$92520221 997 $aUNINA