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[null,"1.","Record Nr.",null,"UNINA9910299571203321"]
[null,null,"Autore",null,"Wang Zheng"]
[null,null,"Titolo",null,"High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip / / by Zheng Wang, Anupam Chattopadhyay"]
[null,null,"Pubbl/distr/stampa",null,"Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2018"]
[null,null,"ISBN",null,"981-10-1073-0"]
[null,null,"Edizione",null,"[1st ed. 2018.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XX, 197 p. 104 illus., 72 illus. in color.)"]
[null,null,"Collana",null,"Computer Architecture and Design Methodologies, , 2367-3486"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Computers"]
[{"$nulls":4},"Electronic Circuits and Systems"]
[{"$nulls":4},"Hardware Performance and Reliability"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references."]
[null,null,"Nota di contenuto",null,"Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook."]
[null,null,null,"Sommario/riassunto","This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. ."]