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IMFEDK 2014 : 2014 International Meeting for Future of Electron Devices, Kansai : June 19-20, 2014, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others]
| IMFEDK 2014 : 2014 International Meeting for Future of Electron Devices, Kansai : June 19-20, 2014, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 |
| Descrizione fisica | 1 online resource (137 pages) |
| Disciplina | 621.39 |
| Soggetto topico |
Digital electronics
Semiconductors |
| ISBN | 1-4799-3615-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910141900603321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IMFEDK 2015 : 2015 International Meeting for Future of Electron Devices, Kansai : June 4-5, 2015 : Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others]
| IMFEDK 2015 : 2015 International Meeting for Future of Electron Devices, Kansai : June 4-5, 2015 : Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2015 |
| Descrizione fisica | 1 online resource (55 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital electronics
Semiconductors |
| ISBN | 1-4799-8615-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910131506203321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IMFEDK 2015 : 2015 International Meeting for Future of Electron Devices, Kansai : June 4-5, 2015 : Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others]
| IMFEDK 2015 : 2015 International Meeting for Future of Electron Devices, Kansai : June 4-5, 2015 : Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsors, IEEE EDS Kansai Chapter [and seven others] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2015 |
| Descrizione fisica | 1 online resource (55 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital electronics
Semiconductors |
| ISBN | 1-4799-8615-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280022103316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IMFEDK 2018 : 2018 International Meeting for Future of Electron Devices, Kansai : June 21-22, 2018, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsored by IEEE EDS Kansai Chapter
| IMFEDK 2018 : 2018 International Meeting for Future of Electron Devices, Kansai : June 21-22, 2018, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsored by IEEE EDS Kansai Chapter |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (945 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital electronics
Semiconductors |
| ISBN | 1-5386-6341-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910305155003321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IMFEDK 2018 : 2018 International Meeting for Future of Electron Devices, Kansai : June 21-22, 2018, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsored by IEEE EDS Kansai Chapter
| IMFEDK 2018 : 2018 International Meeting for Future of Electron Devices, Kansai : June 21-22, 2018, Ryukoku University Avanti Kyoto Hall, Kyoto, Japan / / sponsored by IEEE EDS Kansai Chapter |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (945 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital electronics
Semiconductors |
| ISBN | 1-5386-6341-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996577956103316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integration : the VLSI journal
| Integration : the VLSI journal |
| Pubbl/distr/stampa | [Amsterdam], : Elsevier Science |
| Soggetto topico |
Integrated circuits - Very large scale integration
Digital electronics Circuits intégrés à très grande échelle Électronique numérique - Périodiques |
| ISSN | 1872-7522 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Integration, the VLSI journal
Integration, the very large scale integration journal VLSI journal Integration: The VLSI Journal |
| Record Nr. | UNISA-996218051403316 |
| [Amsterdam], : Elsevier Science | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integration : the VLSI journal
| Integration : the VLSI journal |
| Pubbl/distr/stampa | [Amsterdam], : Elsevier Science |
| Soggetto topico |
Integrated circuits - Very large scale integration
Digital electronics Circuits intégrés à très grande échelle Électronique numérique - Périodiques |
| ISSN | 1872-7522 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Integration, the VLSI journal
Integration, the very large scale integration journal VLSI journal Integration: The VLSI Journal |
| Record Nr. | UNINA-9910145768503321 |
| [Amsterdam], : Elsevier Science | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
International journal of digital health
| International journal of digital health |
| Pubbl/distr/stampa | [London] : , : IJS Press, part of IJS Publishing Group, , 2021- |
| Disciplina | 610.285 |
| Soggetto topico |
Medical care
Digital electronics |
| Soggetto genere / forma | Periodicals. |
| ISSN | 2634-4580 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910599301303321 |
| [London] : , : IJS Press, part of IJS Publishing Group, , 2021- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to digital systems : modeling, synthesis, and simulation using VHDL / / Mohammed Ferdjallah
| Introduction to digital systems : modeling, synthesis, and simulation using VHDL / / Mohammed Ferdjallah |
| Autore | Ferdjallah Mohammed |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley, , 2011 |
| Descrizione fisica | 1 online resource (227 p.) |
| Disciplina |
621.39/2
621.392 |
| Soggetto topico |
Digital electronics
Digital electronics - Computer simulation VHDL (Computer hardware description language) |
| ISBN |
1-283-13882-4
9786613138828 1-118-00770-0 1-118-00771-9 1-118-00769-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL; CONTENTS; PREFACE; 1 Digital System Modeling and Simulation; 1.1 OBJECTIVES; 1.2 MODELING, SYNTHESIS, AND SIMULATION DESIGN; 1.3 HISTORY OF DIGITAL SYSTEMS; 1.4 STANDARD LOGIC DEVICES; 1.5 CUSTOM-DESIGNED LOGIC DEVICES; 1.6 PROGRAMMABLE LOGIC DEVICES; 1.7 SIMPLE PROGRAMMABLE LOGIC DEVICES; 1.8 COMPLEX PROGRAMMABLE LOGIC DEVICES; 1.9 FIELD-PROGRAMMABLE GATE ARRAYS; 1.10 FUTURE OF DIGITAL SYSTEMS; PROBLEMS; 2 Number Systems; 2.1 OBJECTIVES; 2.2 BASES AND NUMBER SYSTEMS; 2.3 NUMBER CONVERSIONS; 2.4 DATA ORGANIZATION
2.5 SIGNED AND UNSIGNED NUMBERS2.6 BINARY ARITHMETIC; 2.7 ADDITION OF SIGNED NUMBERS; 2.8 BINARY-CODED DECIMAL REPRESENTATION; 2.9 BCD ADDITION; PROBLEMS; 3 Boolean Algebra and Logic; 3.1 OBJECTIVES; 3.2 BOOLEAN THEORY; 3.3 LOGIC VARIABLES AND LOGIC FUNCTIONS; 3.4 BOOLEAN AXIOMS AND THEOREMS; 3.5 BASIC LOGIC GATES AND TRUTH TABLES; 3.6 LOGIC REPRESENTATIONS AND CIRCUIT DESIGN; 3.7 TRUTH TABLE; 3.8 TIMING DIAGRAM; 3.9 LOGIC DESIGN CONCEPTS; 3.10 SUM-OF-PRODUCTS DESIGN; 3.11 PRODUCT-OF-SUMS DESIGN; 3.12 DESIGN EXAMPLES; 3.13 NAND AND NOR EQUIVALENT CIRCUIT DESIGN 3.14 STANDARD LOGIC INTEGRATED CIRCUITSPROBLEMS; 4 VHDL Design Concepts; 4.1 OBJECTIVES; 4.2 CAD TOOL-BASED LOGIC DESIGN; 4.3 HARDWARE DESCRIPTION LANGUAGES; 4.4 VHDL LANGUAGE; 4.5 VHDL PROGRAMMING STRUCTURE; 4.6 ASSIGNMENT STATEMENTS; 4.7 VHDL DATA TYPES; 4.8 VHDL OPERATORS; 4.9 VHDL SIGNAL AND GENERATE STATEMENTS; 4.10 SEQUENTIAL STATEMENTS; 4.11 LOOPS AND DECISION-MAKING STATEMENTS; 4.12 SUBCIRCUIT DESIGN; 4.13 PACKAGES AND COMPONENTS; PROBLEMS; 5 Integrated Logic; 5.1 OBJECTIVES; 5.2 LOGIC SIGNALS; 5.3 LOGIC SWITCHES; 5.4 NMOS AND PMOS LOGIC GATES; 5.5 CMOS LOGIC GATES 5.6 CMOS LOGIC NETWORKS5.7 PRACTICAL ASPECTS OF LOGIC GATES; 5.8 TRANSMISSION GATES; PROBLEMS; 6 Logic Function Optimization; 6.1 OBJECTIVES; 6.2 LOGIC FUNCTION OPTIMIZATION PROCESS; 6.3 KARNAUGH MAPS; 6.4 TWO-VARIABLE KARNAUGH MAP; 6.5 THREE-VARIABLE KARNAUGH MAP; 6.6 FOUR-VARIABLE KARNAUGH MAP; 6.7 FIVE-VARIABLE KARNAUGH MAP; 6.8 XOR AND NXOR KARNAUGH MAPS; 6.9 INCOMPLETE LOGIC FUNCTIONS; 6.10 QUINE-McCLUSKEY MINIMIZATION; PROBLEMS; 7 Combinational Logic; 7.1 OBJECTIVES; 7.2 COMBINATIONAL LOGIC CIRCUITS; 7.3 MULTIPLEXERS; 7.4 LOGIC DESIGN WITH MULTIPLEXERS; 7.5 DEMULTIPLEXERS; 7.6 DECODERS 7.7 ENCODERS7.8 CODE CONVERTERS; 7.9 ARITHMETIC CIRCUITS; PROBLEMS; 8 Sequential Logic; 8.1 OBJECTIVES; 8.2 SEQUENTIAL LOGIC CIRCUITS; 8.3 LATCHES; 8.4 FLIP-FLOPS; 8.5 REGISTERS; 8.6 COUNTERS; PROBLEMS; 9 Synchronous Sequential Logic; 9.1 OBJECTIVES; 9.2 SYNCHRONOUS SEQUENTIAL CIRCUITS; 9.3 FINITE-STATE MACHINE DESIGN CONCEPTS; 9.4 FINITE-STATE MACHINE SYNTHESIS; 9.5 STATE ASSIGNMENT; 9.6 ONE-HOT ENCODING METHOD; 9.7 FINITE-STATE MACHINE ANALYSIS; 9.8 SEQUENTIAL SERIAL ADDER; 9.9 SEQUENTIAL CIRCUIT COUNTERS; 9.10 STATE OPTIMIZATION; 9.11 ASYNCHRONOUS SEQUENTIAL CIRCUITS; PROBLEMS; INDEX |
| Record Nr. | UNINA-9910139646203321 |
Ferdjallah Mohammed
|
||
| Hoboken, New Jersey : , : Wiley, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to digital systems : modeling, synthesis, and simulation using VHDL / / Mohammed Ferdjallah
| Introduction to digital systems : modeling, synthesis, and simulation using VHDL / / Mohammed Ferdjallah |
| Autore | Ferdjallah Mohammed |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley, , 2011 |
| Descrizione fisica | 1 online resource (227 p.) |
| Disciplina |
621.39/2
621.392 |
| Soggetto topico |
Digital electronics
Digital electronics - Computer simulation VHDL (Computer hardware description language) |
| ISBN |
1-283-13882-4
9786613138828 1-118-00770-0 1-118-00771-9 1-118-00769-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL; CONTENTS; PREFACE; 1 Digital System Modeling and Simulation; 1.1 OBJECTIVES; 1.2 MODELING, SYNTHESIS, AND SIMULATION DESIGN; 1.3 HISTORY OF DIGITAL SYSTEMS; 1.4 STANDARD LOGIC DEVICES; 1.5 CUSTOM-DESIGNED LOGIC DEVICES; 1.6 PROGRAMMABLE LOGIC DEVICES; 1.7 SIMPLE PROGRAMMABLE LOGIC DEVICES; 1.8 COMPLEX PROGRAMMABLE LOGIC DEVICES; 1.9 FIELD-PROGRAMMABLE GATE ARRAYS; 1.10 FUTURE OF DIGITAL SYSTEMS; PROBLEMS; 2 Number Systems; 2.1 OBJECTIVES; 2.2 BASES AND NUMBER SYSTEMS; 2.3 NUMBER CONVERSIONS; 2.4 DATA ORGANIZATION
2.5 SIGNED AND UNSIGNED NUMBERS2.6 BINARY ARITHMETIC; 2.7 ADDITION OF SIGNED NUMBERS; 2.8 BINARY-CODED DECIMAL REPRESENTATION; 2.9 BCD ADDITION; PROBLEMS; 3 Boolean Algebra and Logic; 3.1 OBJECTIVES; 3.2 BOOLEAN THEORY; 3.3 LOGIC VARIABLES AND LOGIC FUNCTIONS; 3.4 BOOLEAN AXIOMS AND THEOREMS; 3.5 BASIC LOGIC GATES AND TRUTH TABLES; 3.6 LOGIC REPRESENTATIONS AND CIRCUIT DESIGN; 3.7 TRUTH TABLE; 3.8 TIMING DIAGRAM; 3.9 LOGIC DESIGN CONCEPTS; 3.10 SUM-OF-PRODUCTS DESIGN; 3.11 PRODUCT-OF-SUMS DESIGN; 3.12 DESIGN EXAMPLES; 3.13 NAND AND NOR EQUIVALENT CIRCUIT DESIGN 3.14 STANDARD LOGIC INTEGRATED CIRCUITSPROBLEMS; 4 VHDL Design Concepts; 4.1 OBJECTIVES; 4.2 CAD TOOL-BASED LOGIC DESIGN; 4.3 HARDWARE DESCRIPTION LANGUAGES; 4.4 VHDL LANGUAGE; 4.5 VHDL PROGRAMMING STRUCTURE; 4.6 ASSIGNMENT STATEMENTS; 4.7 VHDL DATA TYPES; 4.8 VHDL OPERATORS; 4.9 VHDL SIGNAL AND GENERATE STATEMENTS; 4.10 SEQUENTIAL STATEMENTS; 4.11 LOOPS AND DECISION-MAKING STATEMENTS; 4.12 SUBCIRCUIT DESIGN; 4.13 PACKAGES AND COMPONENTS; PROBLEMS; 5 Integrated Logic; 5.1 OBJECTIVES; 5.2 LOGIC SIGNALS; 5.3 LOGIC SWITCHES; 5.4 NMOS AND PMOS LOGIC GATES; 5.5 CMOS LOGIC GATES 5.6 CMOS LOGIC NETWORKS5.7 PRACTICAL ASPECTS OF LOGIC GATES; 5.8 TRANSMISSION GATES; PROBLEMS; 6 Logic Function Optimization; 6.1 OBJECTIVES; 6.2 LOGIC FUNCTION OPTIMIZATION PROCESS; 6.3 KARNAUGH MAPS; 6.4 TWO-VARIABLE KARNAUGH MAP; 6.5 THREE-VARIABLE KARNAUGH MAP; 6.6 FOUR-VARIABLE KARNAUGH MAP; 6.7 FIVE-VARIABLE KARNAUGH MAP; 6.8 XOR AND NXOR KARNAUGH MAPS; 6.9 INCOMPLETE LOGIC FUNCTIONS; 6.10 QUINE-McCLUSKEY MINIMIZATION; PROBLEMS; 7 Combinational Logic; 7.1 OBJECTIVES; 7.2 COMBINATIONAL LOGIC CIRCUITS; 7.3 MULTIPLEXERS; 7.4 LOGIC DESIGN WITH MULTIPLEXERS; 7.5 DEMULTIPLEXERS; 7.6 DECODERS 7.7 ENCODERS7.8 CODE CONVERTERS; 7.9 ARITHMETIC CIRCUITS; PROBLEMS; 8 Sequential Logic; 8.1 OBJECTIVES; 8.2 SEQUENTIAL LOGIC CIRCUITS; 8.3 LATCHES; 8.4 FLIP-FLOPS; 8.5 REGISTERS; 8.6 COUNTERS; PROBLEMS; 9 Synchronous Sequential Logic; 9.1 OBJECTIVES; 9.2 SYNCHRONOUS SEQUENTIAL CIRCUITS; 9.3 FINITE-STATE MACHINE DESIGN CONCEPTS; 9.4 FINITE-STATE MACHINE SYNTHESIS; 9.5 STATE ASSIGNMENT; 9.6 ONE-HOT ENCODING METHOD; 9.7 FINITE-STATE MACHINE ANALYSIS; 9.8 SEQUENTIAL SERIAL ADDER; 9.9 SEQUENTIAL CIRCUIT COUNTERS; 9.10 STATE OPTIMIZATION; 9.11 ASYNCHRONOUS SEQUENTIAL CIRCUITS; PROBLEMS; INDEX |
| Record Nr. | UNINA-9910806881403321 |
|
Ferdjallah Mohammed
|
||
| Hoboken, New Jersey : , : Wiley, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Soggetto topico
-
Digital electronics
(237)
- Computer architecture (28)
- Engineering & Applied Sciences (23)
- Logic design (22)
- System design (21)