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PRIME, 2008 PhD research in microelectronics and electronics : proceedings : Istanbul, Turkey, June 22-25, 2008
| PRIME, 2008 PhD research in microelectronics and electronics : proceedings : Istanbul, Turkey, June 22-25, 2008 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2008 |
| Soggetto topico |
Integrated circuits
Digital electronics Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-5090-8046-5
1-4244-1984-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145729803321 |
| [Place of publication not identified], : IEEE, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principi di elettronica dei sistemi digitali / Angelo Geraci
| Principi di elettronica dei sistemi digitali / Angelo Geraci |
| Autore | Geraci, Angelo |
| Pubbl/distr/stampa | Milano [etc] : McGraw-Hill, c2003 |
| Descrizione fisica | xii, 249 p. : ill. ; 24 cm |
| Disciplina | 621.3815 |
| Collana | Collana di istruzione scientifica. Serie di elettronica |
| Soggetto topico | Digital electronics |
| ISBN | 8838661073 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | ita |
| Record Nr. | UNISALENTO-991003703509707536 |
Geraci, Angelo
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| Milano [etc] : McGraw-Hill, c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Principles of modern digital design [[electronic resource] /] / Parag K. Lala
| Principles of modern digital design [[electronic resource] /] / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina |
621.395
621.39732 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910144576903321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principles of modern digital design [[electronic resource] /] / Parag K. Lala
| Principles of modern digital design [[electronic resource] /] / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina |
621.395
621.39732 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910830744803321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principles of modern digital design [[electronic resource] /] / Parag K. Lala
| Principles of modern digital design [[electronic resource] /] / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina |
621.395
621.39732 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910840962603321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings : 13th Euromicro Conference on Digital System Design : Architectures, Methods, and Tools : Lille, France, 1-3 September 2010
| Proceedings : 13th Euromicro Conference on Digital System Design : Architectures, Methods, and Tools : Lille, France, 1-3 September 2010 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2010 |
| Disciplina | 004.2/2 |
| Soggetto topico |
Digital electronics
System design Computer architecture Engineering & Applied Sciences Computer Science |
| ISBN | 0-7695-4171-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | DSD 2010 |
| Record Nr. | UNISA-996208417203316 |
| [Place of publication not identified], : IEEE Computer Society, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings : 13th Euromicro Conference on Digital System Design : Architectures, Methods, and Tools : Lille, France, 1-3 September 2010
| Proceedings : 13th Euromicro Conference on Digital System Design : Architectures, Methods, and Tools : Lille, France, 1-3 September 2010 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2010 |
| Disciplina | 004.2/2 |
| Soggetto topico |
Digital electronics
System design Computer architecture Engineering & Applied Sciences Computer Science |
| ISBN | 0-7695-4171-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | DSD 2010 |
| Record Nr. | UNINA-9910619140203321 |
| [Place of publication not identified], : IEEE Computer Society, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings : 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia
| Proceedings : 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2006 |
| Soggetto topico |
Digital electronics
System design Computer architecture Engineering & Applied Sciences Computer Science |
| ISBN | 1-5090-9444-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996197735503316 |
| [Place of publication not identified], : IEEE Computer Society, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings : 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia
| Proceedings : 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2006 |
| Soggetto topico |
Digital electronics
System design Computer architecture Engineering & Applied Sciences Computer Science |
| ISBN | 1-5090-9444-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145648803321 |
| [Place of publication not identified], : IEEE Computer Society, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of the 2009 12th EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools : proceedings, 27-29 August 2009, Patras, Greece
| Proceedings of the 2009 12th EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools : proceedings, 27-29 August 2009, Patras, Greece |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2009 |
| Disciplina | 004.22 |
| Soggetto topico |
Digital electronics
System design Computer architecture Engineering & Applied Sciences Computer Science |
| ISBN | 1-5090-7309-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910138779103321 |
| [Place of publication not identified], : IEEE Computer Society, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Soggetto topico
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Digital electronics
(237)
- Computer architecture (28)
- Engineering & Applied Sciences (23)
- Logic design (22)
- System design (21)