Vai al contenuto principale della pagina
Titolo: | Memory Technology, Design and Testing, 1997: IEEE International Workshop on (MTDT '97) |
Pubblicazione: | [Place of publication not identified], : IEEE Computer Society Press, 1997 |
Disciplina: | 621.39/732 |
Soggetto topico: | Semiconductor storage devices - Congresses - Testing |
Random access memory - Congresses | |
Electrical & Computer Engineering | |
Engineering & Applied Sciences | |
Electrical Engineering | |
Persona (resp. second.): | RajsumanRochit |
LombardiFabrizio | |
WikT | |
Note generali: | Bibliographic Level Mode of Issuance: Monograph |
Nota di contenuto: | Matching memory to the power of personal computers / R. Foss -- A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.] -- High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.] -- An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev -- SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen -- False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley -- A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker -- Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant -- A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao -- A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.] -- Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang -- An open notation for memory tests / A. Offerman, A. van de Goor -- Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.] -- Memory array testing through a scannable configuration / S. Yano, N. Ishiura -- A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.]. |
Titolo autorizzato: | Memory Technology, Design and Testing, 1997: IEEE International Workshop on (MTDT '97) |
Formato: | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione: | Inglese |
Record Nr.: | 9910872636003321 |
Lo trovi qui: | Univ. Federico II |
Opac: | Controlla la disponibilità qui |