LEADER 03263oam 2200517zu 450 001 9910872636003321 005 20210807003337.0 035 $a(CKB)111026746745370 035 $a(SSID)ssj0000558514 035 $a(PQKBManifestationID)12198046 035 $a(PQKBTitleCode)TC0000558514 035 $a(PQKBWorkID)10565554 035 $a(PQKB)11690510 035 $a(EXLCZ)99111026746745370 100 $a20160829d1997 uy 101 0 $aeng 181 $ctxt 182 $cc 183 $acr 200 10$aMemory Technology, Design and Testing, 1997: IEEE International Workshop on (MTDT '97) 210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d1997 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a0-8186-8099-7 327 $a Matching memory to the power of personal computers / R. Foss -- A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.] -- High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.] -- An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev -- SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen -- False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley -- A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker -- Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant -- A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao -- A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.] -- Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang -- An open notation for memory tests / A. Offerman, A. van de Goor -- Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.] -- Memory array testing through a scannable configuration / S. Yano, N. Ishiura -- A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.]. 606 $aSemiconductor storage devices$xCongresses$xTesting 606 $aRandom access memory$xCongresses 606 $aElectrical & Computer Engineering$2HILCC 606 $aEngineering & Applied Sciences$2HILCC 606 $aElectrical Engineering$2HILCC 615 0$aSemiconductor storage devices$xCongresses$xTesting 615 0$aRandom access memory$xCongresses 615 7$aElectrical & Computer Engineering 615 7$aEngineering & Applied Sciences 615 7$aElectrical Engineering 676 $a621.39/732 702 $aRajsuman$b Rochit 702 $aLombardi$b Fabrizio 702 $aWik$b T 712 02$aIEEE Computer Society Technical Committee on VLSI, 712 02$aIEEE Computer Society Test Technology Technical Committee 712 12$aIEEE International Workshop on Memory Technology, Design, and Testing 801 0$bPQKB 906 $aBOOK 912 $a9910872636003321 996 $aMemory Technology, Design and Testing, 1997: IEEE International Workshop on (MTDT '97)$92301862 997 $aUNINA