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| Titolo: |
2004 IEEE International High-Level Design Validation and Test Workshop
|
| Pubblicazione: | [Place of publication not identified], : I E E E, 2004 |
| Descrizione fisica: | 1 online resource |
| Disciplina: | 005.14 |
| Soggetto topico: | Computer software - Verification |
| Electronic circuits - Testing | |
| Note generali: | Bibliographic Level Mode of Issuance: Monograph |
| Nota di contenuto: | HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test -- Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) -- Copyright -- Chairs' welcome message -- Committees -- Table of contents -- TTTC: test technology technical council -- Session 1: formal techniques -- Enhancing sequential depth computation with a branch-and-bound algorithm -- Reference model based RTL verification: an integrated approach -- Dynamic guiding of bounded property checking -- Towards an efficient assertion based verification of SystemC designs. |
| Sommario/riassunto: | This page or pages intentionally left blank. |
| Titolo autorizzato: | 2004 IEEE International High-Level Design Validation and Test Workshop ![]() |
| Formato: | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 9910872487603321 |
| Lo trovi qui: | Univ. Federico II |
| Opac: | Controlla la disponibilità qui |