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101 0 $aeng
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181   $ctxt
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183   $acr
200 10$a2004 IEEE International High-Level Design Validation and Test Workshop
210 31$a[Place of publication not identified]$cI E E E$d2004
215   $a1 online resource
300   $aBibliographic Level Mode of Issuance: Monograph
311 08$a9780780387140 
311 08$a0780387147 
327   $aHLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test -- Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) -- Copyright -- Chairs' welcome message -- Committees -- Table of contents -- TTTC: test technology technical council -- Session 1: formal techniques -- Enhancing sequential depth computation with a branch-and-bound algorithm -- Reference model based RTL verification: an integrated approach -- Dynamic guiding of bounded property checking -- Towards an efficient assertion based verification of SystemC designs.
330   $aThis page or pages intentionally left blank.
606   $aComputer software$xVerification$vCongresses
606   $aElectronic circuits$xTesting$vCongresses
615  0$aComputer software$xVerification
615  0$aElectronic circuits$xTesting
676   $a005.14
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906   $aPROCEEDING
912   $a9910872487603321
996   $a2004 IEEE International High-Level Design Validation and Test Workshop$92386429
997   $aUNINA