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Record Nr. |
UNINA9910872487603321 |
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Titolo |
2004 IEEE International High-Level Design Validation and Test Workshop |
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Pubbl/distr/stampa |
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[Place of publication not identified], : I E E E, 2004 |
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Descrizione fisica |
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Disciplina |
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Soggetti |
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Computer software - Verification |
Electronic circuits - Testing |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test -- Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) -- Copyright -- Chairs' welcome message -- Committees -- Table of contents -- TTTC: test technology technical council -- Session 1: formal techniques -- Enhancing sequential depth computation with a branch-and-bound algorithm -- Reference model based RTL verification: an integrated approach -- Dynamic guiding of bounded property checking -- Towards an efficient assertion based verification of SystemC designs. |
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Sommario/riassunto |
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