01986oam 2200433zu 450 991087248760332120241212215431.0(CKB)1000000000278178(SSID)ssj0000454136(PQKBManifestationID)12158199(PQKBTitleCode)TC0000454136(PQKBWorkID)10487947(PQKB)10056857(NjHacI)991000000000278178(EXLCZ)99100000000027817820160829d2004 uy engur|||||||||||txtccr2004 IEEE International High-Level Design Validation and Test Workshop[Place of publication not identified]I E E E20041 online resourceBibliographic Level Mode of Issuance: Monograph9780780387140 0780387147 HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test -- Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) -- Copyright -- Chairs' welcome message -- Committees -- Table of contents -- TTTC: test technology technical council -- Session 1: formal techniques -- Enhancing sequential depth computation with a branch-and-bound algorithm -- Reference model based RTL verification: an integrated approach -- Dynamic guiding of bounded property checking -- Towards an efficient assertion based verification of SystemC designs.This page or pages intentionally left blank.Computer softwareVerificationCongressesElectronic circuitsTestingCongressesComputer softwareVerificationElectronic circuitsTesting005.14PQKBPROCEEDING99108724876033212004 IEEE International High-Level Design Validation and Test Workshop2386429UNINA