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Design Automation Techniques for Approximation Circuits : Verification, Synthesis and Test / / by Arun Chandrasekharan, Daniel Große, Rolf Drechsler
| Design Automation Techniques for Approximation Circuits : Verification, Synthesis and Test / / by Arun Chandrasekharan, Daniel Große, Rolf Drechsler |
| Autore | Chandrasekharan Arun |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (140 pages) |
| Disciplina | 004.21 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-98965-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Preliminaries -- Error Metric Computation for Approximate Combinational Circuits -- Formal Verification of Approximate Sequential Circuits -- Synthesis Techniques for Approximation Circuits -- Post-Production Test Strategies for Approximation Circuits -- ProACt: Hardware Architecture for Cross-Layer Approximate Computing -- Conclusions and Outlook -- Index -- References. |
| Record Nr. | UNINA-9910337646803321 |
Chandrasekharan Arun
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2018 / / edited by Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große
| Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2018 / / edited by Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (197 pages) |
| Disciplina | 004.0151 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-030-31585-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Automatic Generation of Cycle-Accurate Simulink Blocks from HDL IPs -- Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach -- Symbolic Simulation of Dataflow Synchronous Programs with Timers -- Language and Hardware Acceleration Backend for Graph Processing -- Runtime Task Mapping for Lifetime Budgeting in Many-Core Systems -- Fault Analysis in Analog Circuits through Language Manipulation and Abstraction -- Towards Consistency Checking Between HDL and UPF Descriptions. |
| Record Nr. | UNINA-9910366616303321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2017 / / edited by Daniel Große, Sara Vinco, Hiren Patel
| Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2017 / / edited by Daniel Große, Sara Vinco, Hiren Patel |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (130 pages) |
| Disciplina |
621.3815
621.392 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-030-02215-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1. Automatic Integration of HDL IPs in Simulinkusing FMI and S-Function Interfaces -- 2. Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach -- 3. Symbolic Simulation of Dataflow Synchronous Programs with Timers -- 4. Language and Hardware Acceleration Backend for Graph Processing -- 5. Fault Analysis in Analog Circuits through Language Manipulation and Abstraction -- 6. A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. |
| Record Nr. | UNINA-9910337599303321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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