CMOS Test and Evaluation : A Physical Perspective / / by Manjul Bhushan, Mark B. Ketchen
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| Autore: |
Bhushan Manjul
|
| Titolo: |
CMOS Test and Evaluation : A Physical Perspective / / by Manjul Bhushan, Mark B. Ketchen
|
| Pubblicazione: | New York, NY : , : Springer New York : , : Imprint : Springer, , 2015 |
| Edizione: | 1st ed. 2015. |
| Descrizione fisica: | 1 online resource (431 p.) |
| Disciplina: | 537.622 |
| 620 | |
| 621.381 | |
| 621.3815 | |
| Soggetto topico: | Electronics |
| Microelectronics | |
| Electronic circuits | |
| Semiconductors | |
| Quality control | |
| Reliability | |
| Industrial safety | |
| Electronics and Microelectronics, Instrumentation | |
| Circuits and Systems | |
| Quality Control, Reliability, Safety and Risk | |
| Persona (resp. second.): | KetchenMark B |
| Note generali: | Description based upon print version of record. |
| Nota di bibliografia: | Includes bibliographical references and index. |
| Nota di contenuto: | Introduction -- CMOS Circuit Basics -- CMOS Storage Elements and Synchronous Logic -- IDDQ and Power -- Embedded PVT Monitors -- Variability -- Product Chip Test and Characterization -- Reliability, Burn-In and Guardbands -- Data Analysis and Characterization -- CMOS Metrics and Model Evaluation. |
| Sommario/riassunto: | This book extends test structure applications described in Microelectronic Test Structures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters. |
| Titolo autorizzato: | CMOS Test and Evaluation |
| ISBN: | 1-4939-1349-2 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 9910299853003321 |
| Lo trovi qui: | Univ. Federico II |
| Opac: | Controlla la disponibilità qui |