Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE
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| Titolo: |
Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE
|
| Pubblicazione: | Piscataway, NJ : , : IEEE, , 2004 |
| Edizione: | IEC 61523-3 First edition 2004-09 IEEE 1497. |
| Descrizione fisica: | 1 online resource (14 pages) |
| Disciplina: | 629.83 |
| Soggetto topico: | Automatic timers |
| Timing circuits | |
| Electric standards | |
| Sommario/riassunto: | The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementers of tools supporting the format, but anyone with a need to understand the formats contents will find it useful. |
| Altri titoli varianti: | 61523-3-2004 - IEC 61523-3 Ed.1 |
| IEC 61523-3 First edition 2004-09; IEEE 1497 | |
| IEC 61523-3 Ed.1 | |
| Titolo autorizzato: | Delay and Power Calculation Standards |
| ISBN: | 0-7381-4522-X |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 996279339503316 |
| Lo trovi qui: | Univ. di Salerno |
| Opac: | Controlla la disponibilità qui |
Serie:
IEEE Std ; ; 1497(TM)-2001.