LEADER 01927nam 2200445 450 001 996279339503316 005 20231206213936.0 010 $a0-7381-4522-X 035 $a(CKB)3710000000575725 035 $a(NjHacI)993710000000575725 035 $a(EXLCZ)993710000000575725 100 $a20231206d2004 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aDelay and Power Calculation Standards$hPart 3, $iStandard Delay Format (SDF) for the Electronic Design Process /$fIEEE 205 $aIEC 61523-3 First edition 2004-09 IEEE 1497. 210 1$aPiscataway, NJ :$cIEEE,$d2004. 215 $a1 online resource (14 pages) 225 1 $aIEEE Std 1497(TM)-2001 330 $aThe Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementers of tools supporting the format, but anyone with a need to understand the formats contents will find it useful. 410 0$aIEEE Std ;$v1497(TM)-2001. 517 $a61523-3-2004 - IEC 61523-3 Ed.1 517 $aIEC 61523-3 First edition 2004-09; IEEE 1497 517 $aIEC 61523-3 Ed.1 606 $aAutomatic timers 606 $aTiming circuits 606 $aElectric standards 615 0$aAutomatic timers. 615 0$aTiming circuits. 615 0$aElectric standards. 676 $a629.83 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996279339503316 996 $aDelay and Power Calculation Standards$93646236 997 $aUNISA