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Verilog Coding for Logic Synthesis



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Autore: Lee Weng Fook Visualizza persona
Titolo: Verilog Coding for Logic Synthesis Visualizza cluster
Pubblicazione: [Place of publication not identified], : Wiley Interscience Imprint, 2003
Edizione: 1st edition
Descrizione fisica: 1 online resource (1 v.) : ill
Disciplina: 621.395
Soggetto topico: Digital electronics
Logic circuits - Computer-aided design
Verilog (Computer hardware description language)
Note generali: Bibliographic Level Mode of Issuance: Monograph
Nota di bibliografia: Includes bibliographical references and index.
Nota di contenuto: Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface.
Sommario/riassunto: Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses
Titolo autorizzato: Verilog Coding for Logic Synthesis  Visualizza cluster
ISBN: 1-280-55652-8
9786610556526
0-471-45755-8
0-470-35692-8
0-471-45756-6
Formato: Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione: Inglese
Record Nr.: 9910831077603321
Lo trovi qui: Univ. Federico II
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