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Record Nr. |
UNINA9910831077603321 |
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Autore |
Lee Weng Fook |
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Titolo |
Verilog Coding for Logic Synthesis |
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Pubbl/distr/stampa |
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[Place of publication not identified], : Wiley Interscience Imprint, 2003 |
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ISBN |
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1-280-55652-8 |
9786610556526 |
0-471-45755-8 |
0-470-35692-8 |
0-471-45756-6 |
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Edizione |
[1st edition] |
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Descrizione fisica |
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1 online resource (1 v.) : ill |
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Disciplina |
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Soggetti |
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Digital electronics |
Logic circuits - Computer-aided design |
Verilog (Computer hardware description language) |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. |
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Sommario/riassunto |
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Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses |
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