IEEE Std 1800-2005 : IEEE Standard for System Verilog- Unified Hardware Design, Specification, and Verification Language / / IEEE
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| Titolo: |
IEEE Std 1800-2005 : IEEE Standard for System Verilog- Unified Hardware Design, Specification, and Verification Language / / IEEE
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| Pubblicazione: | [Place of publication not identified] : , : IEEE, , 2005 |
| Descrizione fisica: | 1 online resource |
| Disciplina: | 683 |
| Soggetto topico: | Hardware |
| Graphics | |
| Sommario/riassunto: | This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document. |
| Altri titoli varianti: | 1800-2005 - IEEE Standard for SystemVerilog |
| IEEE Std 1800-2005 | |
| Titolo autorizzato: | IEEE Std 1800-2005 |
| ISBN: | 0-7381-4811-3 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 9910147054003321 |
| Lo trovi qui: | Univ. Federico II |
| Opac: | Controlla la disponibilità qui |