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| Titolo: |
VLSI Algorithms and Architectures [[electronic resource] ] : Aegean Workshop on Computing, Loutraki, Greece, July 8-11, 1986. Proceedings / / edited by Fillia Makedon, Kurt Mehlhorn, T. Papatheodorou, P. Spirakis
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| Pubblicazione: | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1986 |
| Edizione: | 1st ed. 1986. |
| Descrizione fisica: | 1 online resource (X, 330 p.) |
| Disciplina: | 621.3 |
| Soggetto topico: | Electrical engineering |
| Electronics | |
| Microelectronics | |
| Microprocessors | |
| Computers | |
| Electrical Engineering | |
| Electronics and Microelectronics, Instrumentation | |
| Processor Architectures | |
| Computation by Abstract Devices | |
| Persona (resp. second.): | MakedonFillia |
| MehlhornKurt | |
| PapatheodorouT | |
| SpirakisP | |
| Note generali: | Bibliographic Level Mode of Issuance: Monograph |
| Nota di contenuto: | Digital filtering in VLSI -- Two processor scheduling is in NC -- Breaking symmetry in synchronous networks -- Parallel ear decomposition search (EDS) and st-numbering in graphs -- A unifying framework for systolic designs -- Optimal tradeoffs for addition on systolic arrays -- On the connection between hexagonal and unidirectional rectangular systolic arrays -- Lower bounds for sorting on mesh-connected architectures -- Diogenes, circa 1986 ????? ??? ??? ????o ????o?o -- Nonsequential computation and laws of nature -- Linear algorithms for two CMOS layout problems -- Some new results on a restricted channel routing problem -- Efficient modular design of TSC checkers for m-out-of-2m codes -- Vlsi algorithms and pipelined architectures for solving structured linear system -- A high-performance single-chip vlsi signal processor architecture -- Exploiting hierarchy in VLSI design -- A polynomial algorithm for recognizing images of polyhedra -- Parallel tree techniques and code optimization -- AT2-optimal galois field multiplier for VLSI -- Linear and book embeddings of graphs -- Efficient parallel evaluation of straight-line code and arithmetic circuits -- A logarithmic boolean time algorithm for parallel polynomial division -- A polynomial algorithm for recognizing small cutwidth in hypergraphs -- A generalized topological sorting problem -- Combinational static CMOS networks -- Fast and efficient parallel linear programming and linear least squares computations -- On the time required to sum n semigroup elements on a parallel machine with simultaneous writes -- A comparative study of concurrency control methods in B-trees -- Generalized river routing — Algorithms and performance bounds. |
| Titolo autorizzato: | VLSI Algorithms and Architectures ![]() |
| ISBN: | 3-540-38746-3 |
| Formato: | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 996465946303316 |
| Lo trovi qui: | Univ. di Salerno |
| Opac: | Controlla la disponibilità qui |