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[null,"1.","Record Nr.",null,"UNISA996465946303316"]
[null,null,"Titolo",null,"VLSI Algorithms and Architectures [[electronic resource] ] : Aegean Workshop on Computing, Loutraki, Greece, July 8-11, 1986. Proceedings / / edited by Fillia Makedon, Kurt Mehlhorn, T. Papatheodorou, P. Spirakis"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1986"]
[null,null,"ISBN",null,"3-540-38746-3"]
[null,null,"Edizione",null,"[1st ed. 1986.]"]
[null,null,"Descrizione fisica",null,"1 online resource (X, 330 p.)"]
[null,null,"Collana",null,"Lecture Notes in Computer Science, , 0302-9743 ; ; 227"]
[null,null,"Disciplina",null,"621.3"]
[null,null,"Soggetti",null,"Electrical engineering"]
[{"$nulls":4},"Electronics"]
[{"$nulls":4},"Microelectronics"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computers"]
[{"$nulls":4},"Electrical Engineering"]
[{"$nulls":4},"Electronics and Microelectronics, Instrumentation"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"Computation by Abstract Devices"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,"Nota di contenuto",null,"Digital filtering in VLSI -- Two processor scheduling is in NC -- Breaking symmetry in synchronous networks -- Parallel ear decomposition search (EDS) and st-numbering in graphs -- A unifying framework for systolic designs -- Optimal tradeoffs for addition on systolic arrays -- On the connection between hexagonal and unidirectional rectangular systolic arrays -- Lower bounds for sorting on mesh-connected architectures -- Diogenes, circa 1986 ????? ??? ??? ????o ????o?o -- Nonsequential computation and laws of nature -- Linear algorithms for two CMOS layout problems -- Some new results on a restricted channel routing problem -- Efficient modular design of TSC checkers for m-out-of-2m codes -- Vlsi algorithms and pipelined architectures for solving structured linear system -- A high-performance single-chip vlsi signal processor architecture -- Exploiting hierarchy in VLSI design -- A polynomial algorithm for recognizing images of polyhedra -- Parallel tree techniques and code optimization "]
[{"$nulls":4},"-- AT2-optimal galois field multiplier for VLSI -- Linear and book embeddings of graphs -- Efficient parallel evaluation of straight-line code and arithmetic circuits -- A logarithmic boolean time algorithm for parallel polynomial division -- A polynomial algorithm for recognizing small cutwidth in hypergraphs -- A generalized topological sorting problem -- Combinational static CMOS networks -- Fast and efficient parallel linear programming and linear least squares computations -- On the time required to sum n semigroup elements on a parallel machine with simultaneous writes -- A comparative study of concurrency control methods in B-trees -- Generalized river routing — Algorithms and performance bounds."]