LEADER 04513nam 22006855 450 001 996465946303316 005 20200630190013.0 010 $a3-540-38746-3 024 7 $a10.1007/3-540-16766-8 035 $a(CKB)1000000000548908 035 $a(SSID)ssj0000327588 035 $a(PQKBManifestationID)11230512 035 $a(PQKBTitleCode)TC0000327588 035 $a(PQKBWorkID)10303700 035 $a(PQKB)11588899 035 $a(DE-He213)978-3-540-38746-6 035 $a(PPN)155200909 035 $a(EXLCZ)991000000000548908 100 $a20121227d1986 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aVLSI Algorithms and Architectures$b[electronic resource] $eAegean Workshop on Computing, Loutraki, Greece, July 8-11, 1986. Proceedings /$fedited by Fillia Makedon, Kurt Mehlhorn, T. Papatheodorou, P. Spirakis 205 $a1st ed. 1986. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1986. 215 $a1 online resource (X, 330 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v227 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-16766-8 327 $aDigital filtering in VLSI -- Two processor scheduling is in NC -- Breaking symmetry in synchronous networks -- Parallel ear decomposition search (EDS) and st-numbering in graphs -- A unifying framework for systolic designs -- Optimal tradeoffs for addition on systolic arrays -- On the connection between hexagonal and unidirectional rectangular systolic arrays -- Lower bounds for sorting on mesh-connected architectures -- Diogenes, circa 1986 ????? ??? ??? ????o ????o?o -- Nonsequential computation and laws of nature -- Linear algorithms for two CMOS layout problems -- Some new results on a restricted channel routing problem -- Efficient modular design of TSC checkers for m-out-of-2m codes -- Vlsi algorithms and pipelined architectures for solving structured linear system -- A high-performance single-chip vlsi signal processor architecture -- Exploiting hierarchy in VLSI design -- A polynomial algorithm for recognizing images of polyhedra -- Parallel tree techniques and code optimization -- AT2-optimal galois field multiplier for VLSI -- Linear and book embeddings of graphs -- Efficient parallel evaluation of straight-line code and arithmetic circuits -- A logarithmic boolean time algorithm for parallel polynomial division -- A polynomial algorithm for recognizing small cutwidth in hypergraphs -- A generalized topological sorting problem -- Combinational static CMOS networks -- Fast and efficient parallel linear programming and linear least squares computations -- On the time required to sum n semigroup elements on a parallel machine with simultaneous writes -- A comparative study of concurrency control methods in B-trees -- Generalized river routing ? Algorithms and performance bounds. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v227 606 $aElectrical engineering 606 $aElectronics 606 $aMicroelectronics 606 $aMicroprocessors 606 $aComputers 606 $aElectrical Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/T24000 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aComputation by Abstract Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/I16013 615 0$aElectrical engineering. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aMicroprocessors. 615 0$aComputers. 615 14$aElectrical Engineering. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aProcessor Architectures. 615 24$aComputation by Abstract Devices. 676 $a621.3 702 $aMakedon$b Fillia$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMehlhorn$b Kurt$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aPapatheodorou$b T$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aSpirakis$b P$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a996465946303316 996 $aVLSI Algorithms and Architectures$92831123 997 $aUNISA