Designing 2D and 3D network-on-chip architectures / / Konstantinos Tatas [and three others]
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| Autore: |
Tatas Konstantinos
|
| Titolo: |
Designing 2D and 3D network-on-chip architectures / / Konstantinos Tatas [and three others]
|
| Pubblicazione: | New York : , : Springer, , 2014 |
| Edizione: | 1st ed. 2014. |
| Descrizione fisica: | 1 online resource (xiii, 265 pages) : illustrations (some color) |
| Disciplina: | 621.392 |
| Soggetto topico: | Networks on a chip - Design and construction |
| Persona (resp. second.): | SioziosKostas |
| SoudrisDimitrios | |
| JantschAxel | |
| Note generali: | Description based upon print version of record. |
| Nota di bibliografia: | Includes bibliographical references. |
| Nota di contenuto: | Part I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.- Projects on Network-on Chip. |
| Sommario/riassunto: | This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies. · Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; · Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; · Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management. |
| Titolo autorizzato: | Designing 2D and 3D Network-on-Chip Architectures |
| ISBN: | 1-4614-4274-5 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 9910299760503321 |
| Lo trovi qui: | Univ. Federico II |
| Opac: | Controlla la disponibilità qui |