LEADER 03053oam  2200457   450 
001 9910299760503321
005 20190911103512.0
010   $a1-4614-4274-5
024 7 $a10.1007/978-1-4614-4274-5
035   $a(OCoLC)862107984
035   $a(MiFhGG)GVRL6UXN
035   $a(EXLCZ)993710000000024996
100   $a20130709d2014      uy             0
101 0 $aeng
135   $aurun|---uuuua
181   $ctxt
182   $cc
183   $acr
200 10$aDesigning 2D and 3D network-on-chip architectures /$fKonstantinos Tatas [and three others]
205   $a1st ed. 2014.
210  1$aNew York :$cSpringer,$d2014.
215   $a1 online resource (xiii, 265 pages) $cillustrations (some color)
225 0 $aGale eBooks
300   $aDescription based upon print version of record.
311   $a1-4614-4273-7 
320   $aIncludes bibliographical references.
327   $aPart I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.-  Projects on Network-on Chip.
330   $aThis book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.
606   $aNetworks on a chip$xDesign and construction
615  0$aNetworks on a chip$xDesign and construction.
676   $a621.392
700   $aTatas$b Konstantinos$4aut$4http://id.loc.gov/vocabulary/relators/aut$0860938
702   $aSiozios$b Kostas$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aSoudris$b Dimitrios$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aJantsch$b Axel$4aut$4http://id.loc.gov/vocabulary/relators/aut
801  0$bMiFhGG
801  1$bMiFhGG
906   $aBOOK
912   $a9910299760503321
996   $aDesigning 2D and 3D Network-on-Chip Architectures$91921308
997   $aUNINA