Applied reconfigurable computing : architectures, tools, and applications : 18th international symposium, ARC 2022, virtual event, September 19-20, 2022, proceedings / / Lin Gan [and three others], editors

• Pubblicazione: Cham, Switzerland : , : Springer, , [2022]; ©2022
• Descrizione fisica: 1 online resource (207 pages)
• Disciplina: 004
• Soggetto topico: Adaptive computing systems
• Persona (resp. second.): GanLin
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Intro -- Preface -- Organization -- Contents -- 100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs -- 1 Introduction -- 1.1 Related Work -- 2 Background -- 3 Soft Scan-Chain Methodology -- 4 Experimental Results -- References -- FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations -- 1 Introduction -- 2 Background -- 2.1 Classical MD with Tersoff Potential -- 2.2 Prior MD Work -- 3 Efficient Data Transfer -- 3.1 Bandwidth-Friendly Particle Mapping -- 3.2 Zigzagging Buffer Design -- 4 Fixed-Point Design -- 4.1 Dynamic Range Analysis -- 4.2 Precision Analysis -- 5 Custom Dataflow Design -- 6 Evaluation -- 6.1 Environment Setup -- 6.2 Evaluation Performance -- 6.3 Resource Usage Evaluation -- 6.4 Energy Evaluation -- 7 Conclusion -- References -- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA -- 1 Introduction -- 2 CNN-MLPA Architecture -- 2.1 Processing Element -- 2.2 Scheduler -- 2.3 Controller -- 2.4 Configuration Registers -- 3 Evaluation and Results for MLP Operations -- 3.1 Test Platform -- 3.2 CNN-MLPA Configurations -- 3.3 Test Applications -- 3.4 Performance Evaluation of MLP Accelerator -- 3.5 Resource Utilization and Performance Comparison with Other Works -- 4 Accelerator with CNN Feature -- 4.1 Results for Full CNN-MLP Acceleration -- 5 Conclusion -- References -- A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution -- 1 Introduction -- 2 Related Work -- 3 Background Technologies -- 3.1 OpenAI Gym -- 3.2 Versatile Tensor Accelerator -- 3.3 Pyro Library -- 4 Neuroevolutionary Framework Overview -- 4.1 Evolutionary Algorithm Overview -- 4.2 Distribution of Evolutionary Processes -- 5 Detailed SW/HW Architecture of the Neuroevolutionary Agents -- 5.1 Software Subsystem. ; 5.2 Hardware Subsystem -- 6 Experimental Results -- 6.1 Fitness Evaluation -- 6.2 Architecture Evaluation -- 7 Conclusions and Future Work -- References -- Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation -- 1 Introduction -- 2 Typical Works in Early Stage -- 2.1 Optimization Schemes for SW26010 -- 2.2 Typical Applications -- 3 Recently Development Progress -- 3.1 Optimization Works for SW26010Pro -- 3.2 Pre-processing Functions Within SWLBM -- 3.3 Immersed Boundary Conditions -- 3.4 Other Expert Applications with SWLBM -- 4 Conclusions -- References -- Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network -- 1 Introduction -- 2 Background and Related Work -- 3 Early-Exit Topology and Training -- 4 FPGA Optimization and Deployment -- 5 Evaluation -- 5.1 Entropy Threshold Evaluation -- 5.2 Camera Input Evaluation -- 5.3 Performance and Accuracy Evaluation -- 6 Conclusions and Future Work -- References -- FPGA-Extended General Purpose Computer Architecture -- 1 Introduction -- 2 Challenges -- 3 Solution -- 4 Evaluation -- 4.1 Benchmark Classification -- 4.2 Single-Program -- 4.3 Multi-program -- 5 Feasibility -- 5.1 Reconfiguration Latency Representativeness -- 5.2 Bitstream Cache Dimensions -- 6 Related Work -- 7 Conclusions -- References -- Multi-spectral In-Vivo FPGA-Based Surgical Imaging -- 1 Introduction -- 2 Intelligent Surgical System -- 3 Extraction of Tissue Features -- 3.1 Image Acquisition -- 3.2 CLAHE -- 3.3 Convolution with Derivatives of Gaussian Kernel -- 3.4 Constructing the Hessian Matrix -- 3.5 Eigenvalues of Hessian Matrix -- 3.6 Feature Extraction or ROI Function -- 4 FPGA-Based Image Processing System Architecture -- 4.1 Experimental Setup -- 5 Evaluation -- 5.1 Baseline Design -- 5.2 Convolution Optimisations -- 5.3 Combined Designs. ; 5.4 Implementation Comparison -- 6 Conclusions -- References -- Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices -- 1 Introduction -- 2 Background -- 2.1 Neural Networks -- 2.2 Deep Learning on Edge Devices -- 2.3 Parallelization Optimizations Using HLS -- 3 Approach -- 3.1 Design Flow -- 3.2 Optimization Algorithm -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Performance Mode -- 4.3 Compact Mode -- 4.4 Comparison Between Performance and Compact Modes -- 4.5 Comparison with State-of-the-Art -- 4.6 Further Work -- 5 Conclusion -- References -- IPEC: Open-Source Design Automation for Inter-Processing Element Communication -- 1 Introduction -- 2 Fundamentals and Terminology -- 3 Related Work -- 4 Capabilities -- 4.1 Connections -- 4.2 Memory -- 4.3 Dispatch - Starting PEs -- 5 Using IPEC to Simplify SoC Implementation -- 5.1 Device, PEs and Memory -- 5.2 Connections -- 5.3 Locks - Deadlock Avoidance -- 5.4 IPEC Intermediate Representation -- 5.5 Interconnect Generation -- 5.6 Address Map Generation -- 5.7 Advantages of Embedding IPEC in Python -- 6 Evaluation -- 6.1 Case Study I: neoDB Database System -- 6.2 Case Study II: Hardware Fuzzing Accelerator -- 7 Conclusion and Future Work -- References -- Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation -- 1 Introduction -- 2 Background -- 2.1 Data Augmentation -- 2.2 Permutation Generation Network -- 3 Accelerator Architecture -- 3.1 Network Structure -- 3.2 Permutation Selection -- 3.3 Further Optimization -- 4 Evaluation -- 4.1 Effect of Using Different Permutations -- 4.2 Comparison to Existing Data Augmentation Methods -- 4.3 Comparison to Existing Permutation Architectures -- 5 Applications -- 5.1 Inference -- 5.2 Training -- 6 Conclusion -- References. ; Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features -- 1 Introduction -- 2 Object Tracking with Correlation Filters -- 2.1 MOSSE -- 2.2 KCF -- 2.3 DSST -- 2.4 Convolutional Features -- 3 Previous Work -- 4 The Proposed CF Implementation -- 4.1 CNN Quantisation Using Knowledge Transfer -- 4.2 Software Model Evaluation on VOT2015 -- 4.3 Multichannel MOSSE Filter Implementation on FPGA -- 5 Conclusion -- References -- VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms -- 1 Introduction -- 2 Related Work -- 3 VenOS Framework -- 3.1 VenOS Architecture -- 3.2 Memory Node -- 3.3 User Node -- 3.4 Resource Manager -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Resource Overhead -- 4.3 Virtualization Overhead -- 4.4 Performance Scalability of VenOS Architecture -- 4.5 Interference Among Collocated Accelerators -- 5 Conclusions -- References -- Author Index.
• Titolo autorizzato: Applied Reconfigurable Computing
• ISBN: 3-031-19983-9
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 9910624397403321
• Lo trovi qui: Univ. Federico II
• Serie: Lecture notes in computer science ; ; Volume 13569.