Synthesizable VHDL design for FPGAs / / Eduardo Augusto Bezerra, Djones Vinicius Lettnin

• Autore: Bezerra Eduardo Augusto
• Pubblicazione: Cham, Switzerland : , : Springer, , 2014
• Edizione: 1st ed. 2014.
• Descrizione fisica: 1 online resource (vii, 157 pages) : illustrations (some color)
• Disciplina: 005.1; 620; 621.381; 621.3815
• Soggetto topico: VHDL (Computer hardware description language); Field programmable gate arrays
• Persona (resp. second.): LettninDjones Vinicius
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references.
• Nota di contenuto: Digital Systems, FPGAs and the Design Flow -- HDL Based Designs -- Hierarchical Design -- Multiplexer and Demultiplexer -- Code Converters -- Sequential Circuits, Latches and Flip-Flops -- Synthesis of Finite State Machines -- Finite State Machines as Control Modules -- Processes in Details -- Arithmetic Circuits -- VHDL Design Examples for FPGA Synthesis.
• Sommario/riassunto: This book provides a gradual description of very-high-speed integrated circuits hardware description language (VHDL), targeting the design of digital systems to be implemented in field-programmable gate array (FPGA) platforms. It is organized in a very didactic way. The adopted methodology was matured over 20 years of teaching experience in the subject. The examples in the book were planned targeting two FPGA platforms, one used widely around the world and the other one developed by a Brazilian company.
• Titolo autorizzato: Synthesizable VHDL Design for FPGAs
• ISBN: 3-319-02547-3
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 9910299498503321
• Lo trovi qui: Univ. Federico II