Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers
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| Titolo: |
Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers
|
| Pubblicazione: | New York, New York : , : IEEE, , 2004 |
| Descrizione fisica: | 1 online resource |
| Disciplina: | 621.392 |
| Soggetto topico: | Verilog (Computer hardware description language) |
| VHDL (Computer hardware description language) | |
| Sommario/riassunto: | The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. |
| Altri titoli varianti: | 61691-4-2004 - IEC 61691-4 Ed.1 |
| Titolo autorizzato: | Behavioural languages |
| ISBN: | 0-7381-4524-6 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 996575395803316 |
| Lo trovi qui: | Univ. di Salerno |
| Opac: | Controlla la disponibilità qui |
Serie:
IEEE Std ; ; 1364.