IEEE Std 1076.3-1997 : IEEE Standard VHDL Synthesis Packages / / Institute of Electrical and Electronics Engineers
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| Titolo: |
IEEE Std 1076.3-1997 : IEEE Standard VHDL Synthesis Packages / / Institute of Electrical and Electronics Engineers
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| Pubblicazione: | New York : , : IEEE, , 1997 |
| Descrizione fisica: | 1 online resource (52 pages) |
| Disciplina: | 621.38101135133 |
| Soggetto topico: | Computer hardware description languages |
| VHDL (Computer hardware description language) | |
| Sommario/riassunto: | The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications. |
| Altri titoli varianti: | IEEE Std 1076.3-1997 |
| Titolo autorizzato: | IEEE Std 1076.3-1997 |
| ISBN: | 0-7381-0989-4 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 996280512203316 |
| Lo trovi qui: | Univ. di Salerno |
| Opac: | Controlla la disponibilità qui |