LEADER 01951nam  2200373   450 
001 996280512203316
005 20231208095019.0
010   $a0-7381-0989-4
024 7 $a10.1109/IEEESTD.1997.82399
035   $a(CKB)3780000000092633
035   $a(NjHacI)993780000000092633
035   $a(EXLCZ)993780000000092633
100   $a20231208d1997      uy             0
101 0 $aeng
135   $aur|||||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aIEEE Std 1076.3-1997 $eIEEE Standard VHDL Synthesis Packages /$fInstitute of Electrical and Electronics Engineers
210  1$aNew York :$cIEEE,$d1997.
215   $a1 online resource (52 pages)
330   $aThe current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.
517   $aIEEE Std 1076.3-1997
606   $aComputer hardware description languages
606   $aVHDL (Computer hardware description language)
615  0$aComputer hardware description languages.
615  0$aVHDL (Computer hardware description language)
676   $a621.38101135133
801  0$bNjHacI
801  1$bNjHacl
906   $aDOCUMENT
912   $a996280512203316
996   $aIEEE Std 1076.3-1997$93646730
997   $aUNISA