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GLSVLSI '16 : proceedings of the 2016 ACM Great Lakes Symposium on VLSI : May 18-20, 2016, Boston, MA, USA / / sponsored by ACM SIGSAC
| GLSVLSI '16 : proceedings of the 2016 ACM Great Lakes Symposium on VLSI : May 18-20, 2016, Boston, MA, USA / / sponsored by ACM SIGSAC |
| Pubbl/distr/stampa | New York : , : ACM, , 2016 |
| Descrizione fisica | 1 online resource (446 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Computer-aided design Electronic circuit design |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910137081103321 |
| New York : , : ACM, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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GLSVLSI '16 : proceedings of the 2016 ACM Great Lakes Symposium on VLSI : May 18-20, 2016, Boston, MA, USA / / sponsored by ACM SIGSAC
| GLSVLSI '16 : proceedings of the 2016 ACM Great Lakes Symposium on VLSI : May 18-20, 2016, Boston, MA, USA / / sponsored by ACM SIGSAC |
| Pubbl/distr/stampa | New York : , : ACM, , 2016 |
| Descrizione fisica | 1 online resource (446 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Computer-aided design Electronic circuit design |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280962903316 |
| New York : , : ACM, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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GLSVLSI '17 : proceedings of the Great Lakes Symposium on VLSI 2017 : May 10-12, 2017 : Banff, Alberta, Canada / / Association for Computing Machinery
| GLSVLSI '17 : proceedings of the Great Lakes Symposium on VLSI 2017 : May 10-12, 2017 : Banff, Alberta, Canada / / Association for Computing Machinery |
| Pubbl/distr/stampa | New York, NY : , : The Association for Computing Machinery, , [2017] |
| Descrizione fisica | 1 online resource : illustrations |
| Disciplina | 005.8 |
| Soggetto topico |
Computer security
Computer-aided design Electronic circuit design Integrated circuits - Very large scale integration |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910375767203321 |
| New York, NY : , : The Association for Computing Machinery, , [2017] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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GLSVLSI '22 : proceedings of the Great Lakes Symposium on VLSI 2022 : June 6-8, 2022, ,Irvine, CA, USA / / general chairs, Ioannis Savidis, Avesta Sasan
| GLSVLSI '22 : proceedings of the Great Lakes Symposium on VLSI 2022 : June 6-8, 2022, ,Irvine, CA, USA / / general chairs, Ioannis Savidis, Avesta Sasan |
| Pubbl/distr/stampa | New York : , : Association for Computing Machinery, , 2022 |
| Descrizione fisica | 1 online resource (560 pages) : illustrations |
| Disciplina | 621.395 |
| Collana | ACM Conferences |
| Soggetto topico |
Integrated circuits - Very large scale integration
Machine learning Computer security Computer-aided design Electronic circuit design |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910580193103321 |
| New York : , : Association for Computing Machinery, , 2022 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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GLSVLSI'18 : proceedings of the 2018 Great Lakes Symposium on VLSI : May 23-25, 2018, Chicago, IL, USA / / Great Lakes Symposium on VLSI 2018 ; Deming Chen, program chair ; Association for Computing Machinery-Digital Library, contributor
| GLSVLSI'18 : proceedings of the 2018 Great Lakes Symposium on VLSI : May 23-25, 2018, Chicago, IL, USA / / Great Lakes Symposium on VLSI 2018 ; Deming Chen, program chair ; Association for Computing Machinery-Digital Library, contributor |
| Pubbl/distr/stampa | New York NY : , : ACM, , 2018 |
| Descrizione fisica | 1 online resource (183 pages) : illustrations |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Electronic circuit design Computer-aided design Computer security |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910375973203321 |
| New York NY : , : ACM, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi
| Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi |
| Autore | Tehranipoor Mohammad H. <1974-> |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (356 pages) |
| Disciplina | 929.605 |
| Soggetto topico |
Electronic circuits
Electronic circuit design Microprocessors Computer architecture Electronic Circuits and Systems Electronics Design and Verification Processor Architectures |
| ISBN | 3-031-19185-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Hardware Security Primitives and their Applications -- Racetrack PUF -- TERO PUF -- Direct Characterization PUF -- Volatile Memory Based PUF -- Emerging Memory Based PUF -- Extrinsic Characterization of PUF -- Radio PUFs and CoAs -- Optical PUFs -- True Random Number Generators -- Hardware Camouflaging -- Temper Detection Methods -- Embedded Watermarking -- Counterfeit and Recycled IC Detection -- Package-Level Counterfeit IC Detection -- Side Channels Protection in Cryptographic Hardware -- Fault Injection Resistant Cryptographic Hardware -- Energy and Performance Optimization for Cryptography -- Lightweight Cryptography -- Post-Quantum Cryptography -- Virtual Proof of Reality -- Analog Security. |
| Record Nr. | UNINA-9910635396903321 |
Tehranipoor Mohammad H. <1974->
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi
| Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi |
| Autore | Tehranipoor Mark |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (XXIV, 320 p. 250 illus., 218 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Electronic circuit design Electronic Circuits and Systems Embedded Systems Electronics Design and Verification |
| ISBN | 3-031-31034-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Physical Unclonable Functions (PUFs) -- Chapter 2. True Random Number Generator (TRNG) -- Chapter 3. Recycled Chip Detection using RO-based Odometer -- Chapter 4. Recycled FPGA Detection -- Chapter 5. Hardware Trojan Insertion -- Chapter 6. Hardware Trojan Detection -- Chapter 7. Security Verification -- Chapter 8. Power Analysis Attacks on AES -- Chapter 9. EM Side-Channel Attack on AES -- Chapter 10. Logic Locking Insertion and Assessment -- Chapter 11. Clock Glitch Fault Attack on FSM in AES Controller -- Chapter 12. Voltage Glitch Attack on an FPGA AES Implementation -- Chapter 13. Laser Fault Injection Attack (FIA) -- Chapter 14. Optical Probing Attack on Logic Locking -- Chapter 15. Universal Fault Sensor -- Chapter 16. Scanning Electron Microscope Training. |
| Record Nr. | UNINA-9910742492103321 |
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Tehranipoor Mark
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Heterojunction bipolar transistors for circuit design : microwave modelling and parameter extraction / / Jianjun Gao
| Heterojunction bipolar transistors for circuit design : microwave modelling and parameter extraction / / Jianjun Gao |
| Autore | Gao Jianjun <1968-> |
| Pubbl/distr/stampa | Singapore : , : John Wiley and Sons, Incorporated, , 2015 |
| Descrizione fisica | 1 online resource (278 p.) |
| Disciplina | 621.3815/28 |
| Soggetto topico |
Bipolar transistors
Heterojunctions Electronic circuit design Microwave measurements |
| ISBN |
1-118-92153-4
1-118-92155-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title Page; Copyright Page; Contents; About the Author; Preface; Acknowledgments; Nomenclature; Chapter 1 Introduction; 1.1 Overview of Heterojunction Bipolar Transistors; 1.2 Modeling and Measurement for HBT; 1.3 Organization of This Book; References; Chapter 2 Basic Concept of Microwave Device Modeling; 2.1 Signal Parameters; 2.1.1 Low-Frequency Parameters; 2.1.2 S-Parameters; 2.2 Representation of Noisy Two-Port Network; 2.2.1 Noise Matrix; 2.2.2 Noise Parameters; 2.3 Basic Circuit Elements; 2.3.1 Resistance; 2.3.2 Capacitance; 2.3.3 Inductance; 2.3.4 Controlled Sources
2.3.5 Ideal Transmission Line2.4 π- and T-Type Networks; 2.4.1 T-Type Network; 2.4.2 π-Type Network; 2.4.3 Relationship between π- and T-Type Networks; 2.5 Deembedding Method; 2.5.1 Parallel Deembedding; 2.5.2 Series Deembedding; 2.5.3 Cascading Deembedding; 2.6 Basic Methods of Parameter Extraction; 2.6.1 Determination of Capacitance; 2.6.2 Determination of Inductance; 2.6.3 Determination of Resistance; 2.7 Summary; References; Chapter 3 Modeling and Parameter Extraction Methods of Bipolar Junction Transistor; 3.1 PN Junction; 3.2 PN Junction Diode; 3.2.1 Basic Concept 3.2.2 Equivalent Circuit Model3.2.3 Determination of Model Parameters; 3.3 BJT Physical Operation; 3.3.1 Device Structure; 3.3.2 The Modes of Operation; 3.3.3 Base-Width Modulation; 3.3.4 High Injection and Current Crowding; 3.4 Equivalent Circuit Model; 3.4.1 E-M Model; 3.4.2 G-P Model; 3.4.3 Noise Model; 3.5 Microwave Performance; 3.5.1 Transition Frequency; 3.5.2 Common-Emitter Configuration; 3.5.3 Common-Base Configuration; 3.5.4 Common-Collector Configuration; 3.5.5 Summary and Comparisons; 3.6 Summary; References; Chapter 4 Basic Principle of HBT; 4.1 Semiconductor Heterojunction 4.2 HBT Device4.2.1 GaAs HBT; 4.2.2 InP HBT; 4.3 Summary; References; Chapter 5 Small-Signal Modeling and Parameter Extraction of HBT; 5.1 Small-Signal Circuit Model; 5.1.1 Pad Structure; 5.1.2 T-Type Circuit Model; 5.1.3 π-Type Circuit Model; 5.1.4 Unilateral Power Gain; 5.1.5 fT and fmax; 5.2 HBT Device Structure; 5.3 Extraction Method of PAD Capacitances; 5.3.1 Open Test Structure Method; 5.3.2 Pinch-Off Method; 5.4 Extraction Method of Extrinsic Inductances; 5.4.1 Short Test Structure Method; 5.4.2 Open-Collector Method; 5.5 Extraction Method of Extrinsic Resistance 5.5.1 Z Parameter Method5.5.2 Cold-HBT Method; 5.5.3 Open-Collector Method; 5.6 Extraction Method of Intrinsic Resistance; 5.6.1 Direct Extraction Method; 5.6.2 Hybrid Method; 5.7 Semianalysis Method; 5.8 Summary; References; Chapter 6 Large-Signal Equivalent Circuit Modeling of HBT; 6.1 Linear and Nonlinear; 6.1.1 Definition; 6.1.2 Nonlinear Lumped Elements; 6.2 Large Signal and Small Signal; 6.3 Thermal Resistance; 6.3.1 Definition; 6.3.2 Equivalent Circuit Model; 6.3.3 Determination of Thermal Resistance; 6.4 Nonlinear HBT Modeling; 6.4.1 VBIC Model; 6.4.2 Agilent Model 6.4.3 Macromodeling Method |
| Record Nr. | UNINA-9910140452403321 |
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Gao Jianjun <1968->
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| Singapore : , : John Wiley and Sons, Incorporated, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Heterojunction bipolar transistors for circuit design : microwave modelling and parameter extraction / / Jianjun Gao
| Heterojunction bipolar transistors for circuit design : microwave modelling and parameter extraction / / Jianjun Gao |
| Autore | Gao Jianjun <1968-> |
| Pubbl/distr/stampa | Singapore : , : John Wiley and Sons, Incorporated, , 2015 |
| Descrizione fisica | 1 online resource (278 p.) |
| Disciplina | 621.3815/28 |
| Soggetto topico |
Bipolar transistors
Heterojunctions Electronic circuit design Microwave measurements |
| ISBN |
1-118-92153-4
1-118-92155-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title Page; Copyright Page; Contents; About the Author; Preface; Acknowledgments; Nomenclature; Chapter 1 Introduction; 1.1 Overview of Heterojunction Bipolar Transistors; 1.2 Modeling and Measurement for HBT; 1.3 Organization of This Book; References; Chapter 2 Basic Concept of Microwave Device Modeling; 2.1 Signal Parameters; 2.1.1 Low-Frequency Parameters; 2.1.2 S-Parameters; 2.2 Representation of Noisy Two-Port Network; 2.2.1 Noise Matrix; 2.2.2 Noise Parameters; 2.3 Basic Circuit Elements; 2.3.1 Resistance; 2.3.2 Capacitance; 2.3.3 Inductance; 2.3.4 Controlled Sources
2.3.5 Ideal Transmission Line2.4 π- and T-Type Networks; 2.4.1 T-Type Network; 2.4.2 π-Type Network; 2.4.3 Relationship between π- and T-Type Networks; 2.5 Deembedding Method; 2.5.1 Parallel Deembedding; 2.5.2 Series Deembedding; 2.5.3 Cascading Deembedding; 2.6 Basic Methods of Parameter Extraction; 2.6.1 Determination of Capacitance; 2.6.2 Determination of Inductance; 2.6.3 Determination of Resistance; 2.7 Summary; References; Chapter 3 Modeling and Parameter Extraction Methods of Bipolar Junction Transistor; 3.1 PN Junction; 3.2 PN Junction Diode; 3.2.1 Basic Concept 3.2.2 Equivalent Circuit Model3.2.3 Determination of Model Parameters; 3.3 BJT Physical Operation; 3.3.1 Device Structure; 3.3.2 The Modes of Operation; 3.3.3 Base-Width Modulation; 3.3.4 High Injection and Current Crowding; 3.4 Equivalent Circuit Model; 3.4.1 E-M Model; 3.4.2 G-P Model; 3.4.3 Noise Model; 3.5 Microwave Performance; 3.5.1 Transition Frequency; 3.5.2 Common-Emitter Configuration; 3.5.3 Common-Base Configuration; 3.5.4 Common-Collector Configuration; 3.5.5 Summary and Comparisons; 3.6 Summary; References; Chapter 4 Basic Principle of HBT; 4.1 Semiconductor Heterojunction 4.2 HBT Device4.2.1 GaAs HBT; 4.2.2 InP HBT; 4.3 Summary; References; Chapter 5 Small-Signal Modeling and Parameter Extraction of HBT; 5.1 Small-Signal Circuit Model; 5.1.1 Pad Structure; 5.1.2 T-Type Circuit Model; 5.1.3 π-Type Circuit Model; 5.1.4 Unilateral Power Gain; 5.1.5 fT and fmax; 5.2 HBT Device Structure; 5.3 Extraction Method of PAD Capacitances; 5.3.1 Open Test Structure Method; 5.3.2 Pinch-Off Method; 5.4 Extraction Method of Extrinsic Inductances; 5.4.1 Short Test Structure Method; 5.4.2 Open-Collector Method; 5.5 Extraction Method of Extrinsic Resistance 5.5.1 Z Parameter Method5.5.2 Cold-HBT Method; 5.5.3 Open-Collector Method; 5.6 Extraction Method of Intrinsic Resistance; 5.6.1 Direct Extraction Method; 5.6.2 Hybrid Method; 5.7 Semianalysis Method; 5.8 Summary; References; Chapter 6 Large-Signal Equivalent Circuit Modeling of HBT; 6.1 Linear and Nonlinear; 6.1.1 Definition; 6.1.2 Nonlinear Lumped Elements; 6.2 Large Signal and Small Signal; 6.3 Thermal Resistance; 6.3.1 Definition; 6.3.2 Equivalent Circuit Model; 6.3.3 Determination of Thermal Resistance; 6.4 Nonlinear HBT Modeling; 6.4.1 VBIC Model; 6.4.2 Agilent Model 6.4.3 Macromodeling Method |
| Record Nr. | UNINA-9910822337003321 |
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Gao Jianjun <1968->
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| Singapore : , : John Wiley and Sons, Incorporated, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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High performance multi-channel high-speed I/O circuits / / Taehyoun Oh, Ramesh Harjani
| High performance multi-channel high-speed I/O circuits / / Taehyoun Oh, Ramesh Harjani |
| Autore | Oh Taehyoun |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (x, 89 pages) : illustrations (some color) |
| Disciplina | 621.3822 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Signal processing
Electronic circuit design Electromagnetic interference - Prevention Crosstalk - Prevention |
| ISBN | 1-4614-4963-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling. |
| Record Nr. | UNINA-9910299745103321 |
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Oh Taehyoun
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| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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