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Biblioteca

MARC Lista (tabellare)
ATM quality of service tests for digitized video using ATM over satellite: laboratory tests / / William D. Ivancic, David E. Brooks and Brian D. Frantz
ATM quality of service tests for digitized video using ATM over satellite: laboratory tests / / William D. Ivancic, David E. Brooks and Brian D. Frantz
Autore Ivancic William D.
Pubbl/distr/stampa Cleveland, Ohio : , : National Aeronautics and Space Administration, Lewis Research Center, , July 1997
Descrizione fisica 1 online resource (5 pages) : illustrations
Collana NASA technical memorandum
Soggetto topico Asynchronous transfer mode
Digital systems
Digital data
Video signals
Satellite communication
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti ATM quality of service tests for digitized video using ATM over satellite
Record Nr. UNINA-9910707879003321
Ivancic William D.  
Cleveland, Ohio : , : National Aeronautics and Space Administration, Lewis Research Center, , July 1997
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ATM Signalling : protocols and practice / / Hartmut Brandt, Christian Hapke
ATM Signalling : protocols and practice / / Hartmut Brandt, Christian Hapke
Autore Brandt Hartmut <1963->
Pubbl/distr/stampa Chichester, West Sussex, England : , : John Wiley & Sons, LTD, , 2001
Descrizione fisica 1 online resource (272 p.)
Disciplina 621.3822
Soggetto topico Asynchronous transfer mode
Signals and signaling
ISBN 1-280-55509-2
9786610555093
0-470-85337-9
0-470-84168-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto ATM Signalling PROTOCOLS AND PRACTICE; Contents; Preface; Abbreviations; 1 Introduction; 2 Overview of ATM Signalling; 3 UNI: User-Network Interface; 4 ATM Addresses; 5 SAAL: Signalling ATM Adaptation Layer; 6 PNNI: Private Network Node Interface; 7 ILMI: Integrated Local Management Interface; 8 Protocols on Top of ATM Signalling; Appendix A ITU-T Standards; Appendix B Source Code Availability; References; Index
Record Nr. UNINA-9910146075203321
Brandt Hartmut <1963->  
Chichester, West Sussex, England : , : John Wiley & Sons, LTD, , 2001
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Convergence technologies for 3G networks [[electronic resource] ] : IP, UMTS, EGPRS and ATM / / Jeffrey Bannister, Paul Mather and Sebastian Coope
Convergence technologies for 3G networks [[electronic resource] ] : IP, UMTS, EGPRS and ATM / / Jeffrey Bannister, Paul Mather and Sebastian Coope
Autore Bannister Jeffrey
Pubbl/distr/stampa Chichester, : Wiley, c2004
Descrizione fisica 1 online resource (672 p.)
Disciplina 621.38456
Altri autori (Persone) MatherPaul M
CoopeSebastian
Soggetto topico Universal Mobile Telecommunications System
Computer network protocols
Asynchronous transfer mode
ISBN 1-280-27116-7
9786610271160
0-470-30022-1
0-470-86092-8
0-470-86093-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Convergence Technologies for 3G Networks; Contents; About the Authors; 1 Introduction; 1.1 Background to Convergence; 1.2 Third Generation (3G); 1.3 Why UMTS?; 1.4 IMT2000 Process; 1.5 Organization of the Book; 2 Principles of Communications; 2.1 Circuit- and Packet Switched Data; 2.1.1 Datagram Approach; 2.1.2 Virtual Circuits; 2.2 Analogue and Digital Communications; 2.2.1 Representing Analogue Signals in Digital Format; 2.3 Voice and Video Transmission; 2.3.1 Sampling; 2.3.2 Coding and CODECs; 2.3.3 Pulse Code Modulation; 2.3.4 Compression
2.3.5 Comfort Noise Generation and Activity Detection2.3.6 Packetization Delay; 2.3.7 Erlang and Network Capacity; 2.3.8 Voice over IP (VoIP); 2.3.9 Quality of Service; 2.4 Multiple Access; 2.5 Frequency Division Multiple Access (FDMA); 2.6 Time Division Multiple Access (TDMA); 2.7 Code Division Multiple Access (CDMA); 2.7.1 DS-CDMA Signal Spreading; 2.7.2 Orthogonal Codes and Signal Separation; 2.7.3 PN Sequences; 2.8 Multipath Propagation and Diversity; 2.8.1 Soft Handover; 2.8.2 Fading and Power Control; 2.9 Protecting the Data; 2.9.1 Convolution Coding; 2.9.2 Interleaving; 2.10 Summary
3 GSM Fundamentals3.1 General Architecture; 3.2 Mobility Management; 3.3 GSM Air Interface; 3.3.1 GSM Multiframes; 3.3.2 Traffic Channel Multiframe; 3.3.3 Control Channel Multiframe; 3.3.4 Frames, Multiframes, Superframes and Hyperframes; 3.4 Timing Advance; 3.5 Initial Connection Procedure; 3.6 Protocols and Signalling; 3.7 GSM and Signalling System 7; 3.7.1 Signalling Points; 3.7.2 Protocol Stack for SS7 Signalling over MTP; 3.7.3 Address Translation; 3.7.4 Example of Routing of a Call to a Mobile Subscriber; 3.7.5 Example of Routing of an SMS Message to a Mobile Subscriber; 3.8 Summary
4 General Packet Radio Service4.1 Introduction to GPRS; 4.2 General Architecture; 4.3 GPRS Network Elements; 4.3.1 Serving GPRS Support Node (SGSN); 4.3.2 Gateway GPRS Support Node (GGSN); 4.3.3 Charging Gateway (CG); 4.3.4 Lawful Interception Gateway (LIG); 4.3.5 Domain Name System (DNS); 4.3.6 Border Gateway (BG); 4.4 Network Interfaces; 4.4.1 Network Operation Mode; 4.5 GPRS Air Interface; 4.5.1 Resource Sharing; 4.5.2 Air Interface Coding Schemes; 4.5.3 Classes of Devices; 4.5.4 Advantages of GPRS Over the Air; 4.6 GPRS Protocols; 4.6.1 Physical and Logical Channels
4.6.2 Subnetwork-Dependent Convergence Protocol (SNDCP)4.6.3 Logical Link Control (LLC); 4.6.4 Radio Link Control/Media Access Control (RLC/MAC); 4.6.5 GPRS Radio Protocol; 4.6.6 Layer 1; 4.7 Gb Interface Protocols; 4.7.1 Layer 1 Bis; 4.7.2 Frame Relay; 4.7.3 Base Station System GPRS Protocol (BSSGP); 4.8 GPRS Tunnelling Protocol (GTP); 4.9 Connection Management; 4.9.1 Mobility Management; 4.9.2 Session Management; 4.9.3 Transparent and Non-transparent Mode; 4.9.4 Access Point Name (APN); 4.9.5 Charging and Billing; 4.9.6 QoS over the GPRS Network; 4.10 Connection scenarios
4.11 Other Cellular High-Speed Data Technologies
Record Nr. UNINA-9910143475703321
Bannister Jeffrey  
Chichester, : Wiley, c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Convergence technologies for 3G networks : IP, UMTS, EGPRS and ATM / / Jeffrey Bannister, Paul Mather and Sebastian Coope
Convergence technologies for 3G networks : IP, UMTS, EGPRS and ATM / / Jeffrey Bannister, Paul Mather and Sebastian Coope
Autore Bannister Jeffrey
Edizione [1st ed.]
Pubbl/distr/stampa Chichester, : Wiley, c2004
Descrizione fisica 1 online resource (672 p.)
Disciplina 621.38456
Altri autori (Persone) MatherPaul M
CoopeSebastian
Soggetto topico Universal Mobile Telecommunications System
Computer network protocols
Asynchronous transfer mode
ISBN 9786610271160
9781280271168
1280271167
9780470300220
0470300221
9780470860922
0470860928
9780470860939
0470860936
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Convergence Technologies for 3G Networks; Contents; About the Authors; 1 Introduction; 1.1 Background to Convergence; 1.2 Third Generation (3G); 1.3 Why UMTS?; 1.4 IMT2000 Process; 1.5 Organization of the Book; 2 Principles of Communications; 2.1 Circuit- and Packet Switched Data; 2.1.1 Datagram Approach; 2.1.2 Virtual Circuits; 2.2 Analogue and Digital Communications; 2.2.1 Representing Analogue Signals in Digital Format; 2.3 Voice and Video Transmission; 2.3.1 Sampling; 2.3.2 Coding and CODECs; 2.3.3 Pulse Code Modulation; 2.3.4 Compression
2.3.5 Comfort Noise Generation and Activity Detection2.3.6 Packetization Delay; 2.3.7 Erlang and Network Capacity; 2.3.8 Voice over IP (VoIP); 2.3.9 Quality of Service; 2.4 Multiple Access; 2.5 Frequency Division Multiple Access (FDMA); 2.6 Time Division Multiple Access (TDMA); 2.7 Code Division Multiple Access (CDMA); 2.7.1 DS-CDMA Signal Spreading; 2.7.2 Orthogonal Codes and Signal Separation; 2.7.3 PN Sequences; 2.8 Multipath Propagation and Diversity; 2.8.1 Soft Handover; 2.8.2 Fading and Power Control; 2.9 Protecting the Data; 2.9.1 Convolution Coding; 2.9.2 Interleaving; 2.10 Summary
3 GSM Fundamentals3.1 General Architecture; 3.2 Mobility Management; 3.3 GSM Air Interface; 3.3.1 GSM Multiframes; 3.3.2 Traffic Channel Multiframe; 3.3.3 Control Channel Multiframe; 3.3.4 Frames, Multiframes, Superframes and Hyperframes; 3.4 Timing Advance; 3.5 Initial Connection Procedure; 3.6 Protocols and Signalling; 3.7 GSM and Signalling System 7; 3.7.1 Signalling Points; 3.7.2 Protocol Stack for SS7 Signalling over MTP; 3.7.3 Address Translation; 3.7.4 Example of Routing of a Call to a Mobile Subscriber; 3.7.5 Example of Routing of an SMS Message to a Mobile Subscriber; 3.8 Summary
4 General Packet Radio Service4.1 Introduction to GPRS; 4.2 General Architecture; 4.3 GPRS Network Elements; 4.3.1 Serving GPRS Support Node (SGSN); 4.3.2 Gateway GPRS Support Node (GGSN); 4.3.3 Charging Gateway (CG); 4.3.4 Lawful Interception Gateway (LIG); 4.3.5 Domain Name System (DNS); 4.3.6 Border Gateway (BG); 4.4 Network Interfaces; 4.4.1 Network Operation Mode; 4.5 GPRS Air Interface; 4.5.1 Resource Sharing; 4.5.2 Air Interface Coding Schemes; 4.5.3 Classes of Devices; 4.5.4 Advantages of GPRS Over the Air; 4.6 GPRS Protocols; 4.6.1 Physical and Logical Channels
4.6.2 Subnetwork-Dependent Convergence Protocol (SNDCP)4.6.3 Logical Link Control (LLC); 4.6.4 Radio Link Control/Media Access Control (RLC/MAC); 4.6.5 GPRS Radio Protocol; 4.6.6 Layer 1; 4.7 Gb Interface Protocols; 4.7.1 Layer 1 Bis; 4.7.2 Frame Relay; 4.7.3 Base Station System GPRS Protocol (BSSGP); 4.8 GPRS Tunnelling Protocol (GTP); 4.9 Connection Management; 4.9.1 Mobility Management; 4.9.2 Session Management; 4.9.3 Transparent and Non-transparent Mode; 4.9.4 Access Point Name (APN); 4.9.5 Charging and Billing; 4.9.6 QoS over the GPRS Network; 4.10 Connection scenarios
4.11 Other Cellular High-Speed Data Technologies
Record Nr. UNINA-9910810591203321
Bannister Jeffrey  
Chichester, : Wiley, c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Enhancing end-to-end performance of information services over Ka-band global satellite networks / / Kul B. Bhasin [and three others]
Enhancing end-to-end performance of information services over Ka-band global satellite networks / / Kul B. Bhasin [and three others]
Autore Bhasin K. B.
Pubbl/distr/stampa Cleveland, Ohio : , : National Aeronautics and Space Administration, Lewis Research Center, , December 1997
Descrizione fisica 1 online resource (8 pages) : illustrations
Collana NASA/TM
Soggetto topico Satellite networks
Asynchronous transfer mode
Communication networks
Extremely high frequencies
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910705766703321
Bhasin K. B.  
Cleveland, Ohio : , : National Aeronautics and Space Administration, Lewis Research Center, , December 1997
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Gigabit/ATM
Gigabit/ATM
Pubbl/distr/stampa Boston, Mass., USA, : Information Gatekeepers, ©2002-
Disciplina 384
Soggetto topico Gigabit communications
Asynchronous transfer mode
Soggetto genere / forma Periodicals.
ISSN 1541-1222
Formato Materiale a stampa
Livello bibliografico Periodico
Lingua di pubblicazione eng
Record Nr. UNISA-996452243103316
Boston, Mass., USA, : Information Gatekeepers, ©2002-
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Gigabit/ATM
Gigabit/ATM
Pubbl/distr/stampa Boston, Mass., USA, : Information Gatekeepers, ©2002-
Disciplina 384
Soggetto topico Gigabit communications
Asynchronous transfer mode
Réseaux Gigabit
Mode de transfert asynchrone
Soggetto genere / forma Periodicals.
ISSN 1541-1222
Formato Materiale a stampa
Livello bibliografico Periodico
Lingua di pubblicazione eng
Record Nr. UNINA-9910678539903321
Boston, Mass., USA, : Information Gatekeepers, ©2002-
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
High performance switches and routers / / H. Jonathan Chao and Bin Liu
High performance switches and routers / / H. Jonathan Chao and Bin Liu
Autore Chao H. Jonathan <1955->
Pubbl/distr/stampa Hoboken, New Jersey : , : Wiley-Interscience, , c2007
Descrizione fisica 1 online resource (633 p.)
Disciplina 004.66
621.38216
Altri autori (Persone) LiuBin
Soggetto topico Asynchronous transfer mode
Routers (Computer networks)
Computer network protocols
Packet switching (Data transmission)
ISBN 0-470-45072-X
1-280-90010-5
9786610900107
0-470-11395-2
0-470-11394-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGMENTS -- 1 INTRODUCTION -- 1.1 Architecture of the Internet: Present and Future -- 1.2 Router Architectures -- 1.3 Commercial Core Router Examples -- 1.4 Design of Core Routers -- 1.5 IP Network Management -- -- 1.6 Outline of the Book -- 2 IP ADDRESS LOOKUP -- 2.1 Overview -- 2.2 Trie-Based Algorithms -- 2.3 Hardware-Based Schemes -- 2.4 IPv6 Lookup -- 2.5 Comparison -- 3 PACKET CLASSIFICATION -- 3.1 Introduction -- 3.2 Trie-Based Classifications -- 3.3 Geometric Algorithms -- 3.4 Heuristic Algorithms -- 3.5 TCAM-Based Algorithms -- 4 TRAFFIC MANAGEMENT -- 4.1 Quality of Service -- 4.2 Integrated Services -- 4.3 Differentiated Services -- 4.4 Traffic Policing and Shaping -- 4.5 Packet Scheduling -- 4.6 Buffer Management -- 5 BASICS OF PACKET SWITCHING -- 5.1 Fundamental Switching Concept -- 5.2 Switch Fabric Classification -- 5.3 Buffering Strategy in Switching Fabrics -- 5.4 Multiplane Switching and Multistage Switching -- 5.5 Performance of Basic Switches -- 6 SHARED-MEMORY SWITCHES -- 6.1 Linked List Approach -- 6.2 Content Addressable Memory Approach -- 6.3 Space-Time-Space Approach -- 6.4 Scaling the Shared-Memory Switches -- 6.5 Multicast Shared-Memory Switches -- 7 INPUT-BUFFERED SWITCHES -- 7.1 Scheduling in VOQ-Based Switches -- 7.2 Maximum Matching -- 7.3 Maximal Matching -- 7.4 Randomized Matching Algorithms -- 7.5 Frame-based Matching -- 7.6 Stable Matching with Speedup -- 8 BANYAN-BASED SWITCHES -- 8.1 Banyan Networks -- 8.2 Batcher-Sorting Network -- 8.3 Output Contention Resolution Algorithms -- 8.4 The Sunshine Switch -- 8.5 Deflection Routing -- 8.6 Multicast Copy Networks -- 9 KNOCKOUT-BASED SWITCHES -- 9.1 Single-Stage Knockout Switch -- 9.2 Channel Grouping Principle -- 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) -- 9.4 Appendix -- 10 THE ABACUS SWITCH -- 10.1 Basic Architecture -- 10.2 Multicast Contention Resolution Algorithm -- 10.3 Implementation of Input Port Controller.
10.4 Performance -- 10.5 ATM Routing and Concentration (ARC) Chip -- 10.6 Enhanced Abacus Switch -- 10.7 Abacus Switch for Packet Switching -- 11 CROSSPOINT BUFFERED SWITCHES -- 11.1 Combined Input and Crosspoint Buffered Switches -- 11.2 Combined Input and Crosspoint Buffered Switches with VOQ -- 11.3 OCF_OCF: Oldest Cell First Scheduling -- 11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1 -- 11.5 MCBF: Most Critical Buffer First Scheduling -- 12 CLOS-NETWORK SWITCHES -- 12.1 Routing Property of Clos Network Switches -- 12.2 Looping Algorithm -- 12.3 m-Matching Algorithm -- 12.4 Euler Partition Algorithm -- 12.5 Karol's Algorithm -- 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC) -- 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC) -- 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC) -- 12.9 The ATLANTA Switch -- 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme -- 12.11 The Path Switch -- 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH -- 13.1 TrueWay Switch Architecture -- 13.2 Packet Scheduling -- 13.3 Stage-To-Stage Flow Control -- 13.4 Port-To-Port Flow Control -- 13.5 Performance Analysis -- 13.6 Prototype -- 14 LOAD-BALANCED SWITCHES -- 14.1 Birkhoff-Von Neumann Switch -- 14.2 Load-Balanced Birkhoff-von Neumann Switches -- 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service -- 15 OPTICAL PACKET SWITCHES -- 15.1 Opto-Electronic Packet Switches -- 15.2 Optoelectronic Packet Switch Case Study I -- 15.3 Optoelectronic Packet Switch Case Study II -- 15.4 All Optical Packet Switches -- 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case -- 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case -- 16 HIGH-SPEED ROUTER CHIP SET -- 16.1 Network Processors (NPs) -- 16.2 Co-Processors for Packet Classification -- 16.3 Traffic Management Chips -- 16.4 Switching Fabric Chips -- INDEX.
Record Nr. UNINA-9910143692803321
Chao H. Jonathan <1955->  
Hoboken, New Jersey : , : Wiley-Interscience, , c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
High performance switches and routers / / H. Jonathan Chao and Bin Liu
High performance switches and routers / / H. Jonathan Chao and Bin Liu
Autore Chao H. Jonathan <1955->
Pubbl/distr/stampa Hoboken, New Jersey : , : Wiley-Interscience, , c2007
Descrizione fisica 1 online resource (633 p.)
Disciplina 004.66
621.38216
Altri autori (Persone) LiuBin
Soggetto topico Asynchronous transfer mode
Routers (Computer networks)
Computer network protocols
Packet switching (Data transmission)
ISBN 0-470-45072-X
1-280-90010-5
9786610900107
0-470-11395-2
0-470-11394-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGMENTS -- 1 INTRODUCTION -- 1.1 Architecture of the Internet: Present and Future -- 1.2 Router Architectures -- 1.3 Commercial Core Router Examples -- 1.4 Design of Core Routers -- 1.5 IP Network Management -- -- 1.6 Outline of the Book -- 2 IP ADDRESS LOOKUP -- 2.1 Overview -- 2.2 Trie-Based Algorithms -- 2.3 Hardware-Based Schemes -- 2.4 IPv6 Lookup -- 2.5 Comparison -- 3 PACKET CLASSIFICATION -- 3.1 Introduction -- 3.2 Trie-Based Classifications -- 3.3 Geometric Algorithms -- 3.4 Heuristic Algorithms -- 3.5 TCAM-Based Algorithms -- 4 TRAFFIC MANAGEMENT -- 4.1 Quality of Service -- 4.2 Integrated Services -- 4.3 Differentiated Services -- 4.4 Traffic Policing and Shaping -- 4.5 Packet Scheduling -- 4.6 Buffer Management -- 5 BASICS OF PACKET SWITCHING -- 5.1 Fundamental Switching Concept -- 5.2 Switch Fabric Classification -- 5.3 Buffering Strategy in Switching Fabrics -- 5.4 Multiplane Switching and Multistage Switching -- 5.5 Performance of Basic Switches -- 6 SHARED-MEMORY SWITCHES -- 6.1 Linked List Approach -- 6.2 Content Addressable Memory Approach -- 6.3 Space-Time-Space Approach -- 6.4 Scaling the Shared-Memory Switches -- 6.5 Multicast Shared-Memory Switches -- 7 INPUT-BUFFERED SWITCHES -- 7.1 Scheduling in VOQ-Based Switches -- 7.2 Maximum Matching -- 7.3 Maximal Matching -- 7.4 Randomized Matching Algorithms -- 7.5 Frame-based Matching -- 7.6 Stable Matching with Speedup -- 8 BANYAN-BASED SWITCHES -- 8.1 Banyan Networks -- 8.2 Batcher-Sorting Network -- 8.3 Output Contention Resolution Algorithms -- 8.4 The Sunshine Switch -- 8.5 Deflection Routing -- 8.6 Multicast Copy Networks -- 9 KNOCKOUT-BASED SWITCHES -- 9.1 Single-Stage Knockout Switch -- 9.2 Channel Grouping Principle -- 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) -- 9.4 Appendix -- 10 THE ABACUS SWITCH -- 10.1 Basic Architecture -- 10.2 Multicast Contention Resolution Algorithm -- 10.3 Implementation of Input Port Controller.
10.4 Performance -- 10.5 ATM Routing and Concentration (ARC) Chip -- 10.6 Enhanced Abacus Switch -- 10.7 Abacus Switch for Packet Switching -- 11 CROSSPOINT BUFFERED SWITCHES -- 11.1 Combined Input and Crosspoint Buffered Switches -- 11.2 Combined Input and Crosspoint Buffered Switches with VOQ -- 11.3 OCF_OCF: Oldest Cell First Scheduling -- 11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1 -- 11.5 MCBF: Most Critical Buffer First Scheduling -- 12 CLOS-NETWORK SWITCHES -- 12.1 Routing Property of Clos Network Switches -- 12.2 Looping Algorithm -- 12.3 m-Matching Algorithm -- 12.4 Euler Partition Algorithm -- 12.5 Karol's Algorithm -- 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC) -- 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC) -- 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC) -- 12.9 The ATLANTA Switch -- 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme -- 12.11 The Path Switch -- 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH -- 13.1 TrueWay Switch Architecture -- 13.2 Packet Scheduling -- 13.3 Stage-To-Stage Flow Control -- 13.4 Port-To-Port Flow Control -- 13.5 Performance Analysis -- 13.6 Prototype -- 14 LOAD-BALANCED SWITCHES -- 14.1 Birkhoff-Von Neumann Switch -- 14.2 Load-Balanced Birkhoff-von Neumann Switches -- 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service -- 15 OPTICAL PACKET SWITCHES -- 15.1 Opto-Electronic Packet Switches -- 15.2 Optoelectronic Packet Switch Case Study I -- 15.3 Optoelectronic Packet Switch Case Study II -- 15.4 All Optical Packet Switches -- 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case -- 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case -- 16 HIGH-SPEED ROUTER CHIP SET -- 16.1 Network Processors (NPs) -- 16.2 Co-Processors for Packet Classification -- 16.3 Traffic Management Chips -- 16.4 Switching Fabric Chips -- INDEX.
Record Nr. UNINA-9910830119503321
Chao H. Jonathan <1955->  
Hoboken, New Jersey : , : Wiley-Interscience, , c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
High performance switches and routers / / H. Jonathan Chao and Bin Liu
High performance switches and routers / / H. Jonathan Chao and Bin Liu
Autore Chao H. Jonathan <1955->
Pubbl/distr/stampa Hoboken, N.J., : Wiley-Interscience, c2007
Descrizione fisica 1 online resource (633 p.)
Disciplina 621.382/16
Altri autori (Persone) LiuBin
Soggetto topico Asynchronous transfer mode
Routers (Computer networks)
Computer network protocols
Packet switching (Data transmission)
ISBN 9786610900107
9780470450727
047045072X
9781280900105
1280900105
9780470113950
0470113952
9780470113943
0470113944
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGMENTS -- 1 INTRODUCTION -- 1.1 Architecture of the Internet: Present and Future -- 1.2 Router Architectures -- 1.3 Commercial Core Router Examples -- 1.4 Design of Core Routers -- 1.5 IP Network Management -- -- 1.6 Outline of the Book -- 2 IP ADDRESS LOOKUP -- 2.1 Overview -- 2.2 Trie-Based Algorithms -- 2.3 Hardware-Based Schemes -- 2.4 IPv6 Lookup -- 2.5 Comparison -- 3 PACKET CLASSIFICATION -- 3.1 Introduction -- 3.2 Trie-Based Classifications -- 3.3 Geometric Algorithms -- 3.4 Heuristic Algorithms -- 3.5 TCAM-Based Algorithms -- 4 TRAFFIC MANAGEMENT -- 4.1 Quality of Service -- 4.2 Integrated Services -- 4.3 Differentiated Services -- 4.4 Traffic Policing and Shaping -- 4.5 Packet Scheduling -- 4.6 Buffer Management -- 5 BASICS OF PACKET SWITCHING -- 5.1 Fundamental Switching Concept -- 5.2 Switch Fabric Classification -- 5.3 Buffering Strategy in Switching Fabrics -- 5.4 Multiplane Switching and Multistage Switching -- 5.5 Performance of Basic Switches -- 6 SHARED-MEMORY SWITCHES -- 6.1 Linked List Approach -- 6.2 Content Addressable Memory Approach -- 6.3 Space-Time-Space Approach -- 6.4 Scaling the Shared-Memory Switches -- 6.5 Multicast Shared-Memory Switches -- 7 INPUT-BUFFERED SWITCHES -- 7.1 Scheduling in VOQ-Based Switches -- 7.2 Maximum Matching -- 7.3 Maximal Matching -- 7.4 Randomized Matching Algorithms -- 7.5 Frame-based Matching -- 7.6 Stable Matching with Speedup -- 8 BANYAN-BASED SWITCHES -- 8.1 Banyan Networks -- 8.2 Batcher-Sorting Network -- 8.3 Output Contention Resolution Algorithms -- 8.4 The Sunshine Switch -- 8.5 Deflection Routing -- 8.6 Multicast Copy Networks -- 9 KNOCKOUT-BASED SWITCHES -- 9.1 Single-Stage Knockout Switch -- 9.2 Channel Grouping Principle -- 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) -- 9.4 Appendix -- 10 THE ABACUS SWITCH -- 10.1 Basic Architecture -- 10.2 Multicast Contention Resolution Algorithm -- 10.3 Implementation of Input Port Controller.
10.4 Performance -- 10.5 ATM Routing and Concentration (ARC) Chip -- 10.6 Enhanced Abacus Switch -- 10.7 Abacus Switch for Packet Switching -- 11 CROSSPOINT BUFFERED SWITCHES -- 11.1 Combined Input and Crosspoint Buffered Switches -- 11.2 Combined Input and Crosspoint Buffered Switches with VOQ -- 11.3 OCF_OCF: Oldest Cell First Scheduling -- 11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1 -- 11.5 MCBF: Most Critical Buffer First Scheduling -- 12 CLOS-NETWORK SWITCHES -- 12.1 Routing Property of Clos Network Switches -- 12.2 Looping Algorithm -- 12.3 m-Matching Algorithm -- 12.4 Euler Partition Algorithm -- 12.5 Karol's Algorithm -- 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC) -- 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC) -- 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC) -- 12.9 The ATLANTA Switch -- 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme -- 12.11 The Path Switch -- 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH -- 13.1 TrueWay Switch Architecture -- 13.2 Packet Scheduling -- 13.3 Stage-To-Stage Flow Control -- 13.4 Port-To-Port Flow Control -- 13.5 Performance Analysis -- 13.6 Prototype -- 14 LOAD-BALANCED SWITCHES -- 14.1 Birkhoff-Von Neumann Switch -- 14.2 Load-Balanced Birkhoff-von Neumann Switches -- 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service -- 15 OPTICAL PACKET SWITCHES -- 15.1 Opto-Electronic Packet Switches -- 15.2 Optoelectronic Packet Switch Case Study I -- 15.3 Optoelectronic Packet Switch Case Study II -- 15.4 All Optical Packet Switches -- 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case -- 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case -- 16 HIGH-SPEED ROUTER CHIP SET -- 16.1 Network Processors (NPs) -- 16.2 Co-Processors for Packet Classification -- 16.3 Traffic Management Chips -- 16.4 Switching Fabric Chips -- INDEX.
Record Nr. UNINA-9911019409703321
Chao H. Jonathan <1955->  
Hoboken, N.J., : Wiley-Interscience, c2007
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