Demystifying switched-capacitor circuits [[electronic resource] /] / Mingliang (Michael) Liu |
Autore | Liu Michael |
Edizione | [1st ed.] |
Pubbl/distr/stampa | Oxford, : Newnes, 2006 |
Descrizione fisica | 1 online resource (332 p.) |
Disciplina | 621.3815 |
Soggetto topico |
Switched capacitor circuits
Electronic circuits |
ISBN |
1-280-64263-7
9786610642632 0-08-045876-9 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
front cover; copyright; front matter; About the author; table of contents; Preface; body; 1: Basic MOS Device Physics; 1.1 Introduction; Chapter Outline; 1.2 MOS Transistors; Basic Operation; Scaling of MOS Transistors; 1.3 MOSFET Switches; Switch On-Resistance; Charge Injection; 1.4 MOSFET Capacitors; References; 2: Operational Amplifiers; 2.1 Introduction; Chapter Outline; 2.2 Two-Stage Op-Amps; 2.3 Telescopic and Folded-Cascode Op-Amps; Appendix 2.1; References; 3: Switched-Capacitor Building Blocks; 3.1 Introduction; Chapter Outline; 3.2 Switched-Capacitor Resistor Simulation
SC Resistor SimulationsThe Advantages of SC Resistor Simulations; Capacitance Ratios versus Circuit Parameters; 3.3 Switched-Capacitor Integrators; Parasitic-Sensitive SC Integrators; Parasitic-Insensitive SC Integrators; Fully Differential Integrators; 3.4 CMOS Sample-and-Hold Circuits; Performance Parameters; Testing S&H Circuits; CMOS S&H Circuits; 3.5 Switched-Capacitor Interpolators and Decimators; SC Interpolators; SC Decimators; 3.6 Signal-Flow-Graph Analysis of Switched-Capacitor Circuits; Signal-Flow-Graph Analysis; Mason's Rule; Appendix 3.1; References 4: Switched-Capacitor Filters4.1 Introduction; Chapter Outline; 4.2 Low-Order Switched-Capacitor Filters; First-Order SC Filters; Second-Order SC Filters; Area-Efficient High-Q SC Filters; 4.3 High-Order Switched-Capacitor Filters; Realizations of SC Filters; Biquad Ordering and Dynamic Range Scaling; Design Example: An Elliptical Low-Pass SC Filter; 4.4 High-Frequency CMOS Switched-Capacitor Filters; Appendix 4.1; References; 5: Switched-Capacitor Data Converters; 5.1 Introduction; Chapter Outline; 5.2 Performance Parameters of Data Converters; DAC Specifications; ADC Specifications INL, DNL, and Quantization Noise5.3 Nyquist-Rate DACs; Integrated Nyquist-Rate DACs; Nyquist-Rate SC DACs; Matching Accuracy of Data Converters; 5.4 Nyquist-Rate ADCs; Flash ADCs; Two-Step ADCs; Pipelined ADCs; Cyclic ADCs; Successive-Approximation ADCs; 5.5 Oversampling Data Converters; Nyquist Rate versus Oversampling; Noise Shaping and Stability; Types of Modulators; Modulators with Single-Bit Quantization; Modulators with Multibit Quantization; Appendix 5.1; References; 6: Switched-Capacitor DC-DC Converters; 6.1 Introduction; Types of SC DC-DC Converters Applications of SC DC-DC ConvertersChapter Outline; 6.2 Dickson Charge-Pump; Conventional Dickson Charge-Pump; Improved Dickson Charge-Pumps; 6.3 Cross-Coupled SC Step-Up DC-DC Converters; 6.4 SC Step-Down DC-DC Converters; 6.5 Multiple-Gain SC DC-DC Converters; References; 7: Advanced Switched-Capacitor Circuit Techniques; 7.1 Introduction; Chapter Outline; 7.2 Low-Voltage SC Circuits Techniques; The Low-Voltage Challenge; Clock Boosting and Switch Bootstrapping; Switched Op-Amp; 7.3 Accuracy-Enhancement Techniques for SC Circuits; The Imperfect Op-Amp; Autozeroing Correlated Double-Sampling |
Record Nr. | UNINA-9910809962703321 |
Liu Michael | ||
Oxford, : Newnes, 2006 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Design recipes for FPGAs / / Peter Wilson |
Autore | Wilson Peter |
Edizione | [Second edition.] |
Pubbl/distr/stampa | Amsterdam, Netherlands : , : Newnes, , 2016 |
Descrizione fisica | 1 online resource (352 p.) |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays - Design and construction
Field programmable gate arrays - Energy consumption |
ISBN |
9786611120238
0-08-097129-6 1-281-12023-5 0-08-054842-3 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910789494403321 |
Wilson Peter | ||
Amsterdam, Netherlands : , : Newnes, , 2016 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Design recipes for FPGAs / / Peter Wilson |
Autore | Wilson Peter |
Edizione | [Second edition.] |
Pubbl/distr/stampa | Amsterdam, Netherlands : , : Newnes, , 2016 |
Descrizione fisica | 1 online resource (352 p.) |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays - Design and construction
Field programmable gate arrays - Energy consumption |
ISBN |
9786611120238
0-08-097129-6 1-281-12023-5 0-08-054842-3 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910818803503321 |
Wilson Peter | ||
Amsterdam, Netherlands : , : Newnes, , 2016 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
Autore | Wilson Peter R (Peter Robert), <1939-> |
Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
Descrizione fisica | xxii, 289 p. : ill |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
Soggetto genere / forma | Electronic books. |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910464419503321 |
Wilson Peter R (Peter Robert), <1939-> | ||
Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
Autore | Wilson Peter R (Peter Robert), <1939-> |
Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
Descrizione fisica | xxii, 289 p. : ill |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910789492703321 |
Wilson Peter R (Peter Robert), <1939-> | ||
Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
Autore | Wilson Peter R (Peter Robert), <1939-> |
Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
Descrizione fisica | xxii, 289 p. : ill |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910811745003321 |
Wilson Peter R (Peter Robert), <1939-> | ||
Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield |
Autore | Maxfield Clive <1957-> |
Edizione | [1st edition] |
Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
Descrizione fisica | 1 online resource (561 p.) |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays
Gate array circuits |
Soggetto genere / forma | Electronic books. |
ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
Record Nr. | UNINA-9910450547703321 |
Maxfield Clive <1957-> | ||
Amsterdam ; ; London, : Newnes, c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield |
Autore | Maxfield Clive <1957-> |
Edizione | [1st edition] |
Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
Descrizione fisica | 1 online resource (561 p.) |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays
Gate array circuits |
ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
Record Nr. | UNINA-9910783136003321 |
Maxfield Clive <1957-> | ||
Amsterdam ; ; London, : Newnes, c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield |
Autore | Maxfield Clive <1957-> |
Edizione | [1st edition] |
Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
Descrizione fisica | 1 online resource (561 p.) |
Disciplina | 621.395 |
Soggetto topico |
Field programmable gate arrays
Gate array circuits |
ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
Record Nr. | UNINA-9910817698503321 |
Maxfield Clive <1957-> | ||
Amsterdam ; ; London, : Newnes, c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Designing embedded systems with PIC microcontrollers [[electronic resource] ] : principles and applications / / Tim Wilmshurst |
Autore | Wilmshurst Tim |
Edizione | [2nd ed.] |
Pubbl/distr/stampa | Amsterdam, : Newnes, 2010 |
Descrizione fisica | 1 online resource (693 p.) |
Disciplina | 004.16 |
Soggetto topico |
Embedded computer systems - Design and construction
Microprocessors - Design and construction |
Soggetto genere / forma | Electronic books. |
ISBN |
1-282-66610-X
9786612666100 0-08-096184-3 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | section 1. Getting started with embedded systems -- section 2. Minimum systems and the PIC 16F84A -- section 3. Larger systems and the PIC 16F873A -- section 4. Smarter systems and the PIC 18F2420 -- section 5. Where can we go from here? : distributed systems, bigger systems. |
Record Nr. | UNINA-9910456671103321 |
Wilmshurst Tim | ||
Amsterdam, : Newnes, 2010 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|