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Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 20th International Conference, SAMOS 2020, Samos, Greece, July 5–9, 2020, Proceedings / / edited by Alex Orailoglu, Matthias Jung, Marc Reichenbach
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 20th International Conference, SAMOS 2020, Samos, Greece, July 5–9, 2020, Proceedings / / edited by Alex Orailoglu, Matthias Jung, Marc Reichenbach |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XIII, 372 p. 45 illus.) |
| Disciplina | 004.16 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Software engineering Computer networks Artificial intelligence Computer System Implementation Computer Hardware Software Engineering Computer Communication Networks Artificial Intelligence |
| ISBN | 3-030-60939-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Fast Performance Estimation and Design Space Exploration of SSD Using AI Techniques -- Combining Task- and Data-level Parallelism for High-throughput CNN Inference on Embedded CPUs-GPUs MPSoCs -- AMAIX: A Generic Analytical Model for Deep Learning Accelerators -- Data Mining in System-Level Design Space Exploration of Embedded Systems -- CoPTA: Contiguous Pattern Speculating TLB Architecture -- A Fine-Granularity Image Pyramid Accelerator for Embedded Processors -- Rec2Poly: Converting Recursions to Polyhedral Optimized Loops Using an Inspector-Executor Strategy -- DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator -- Transpiling Python to Rust for Optimized Performance -- A Fast Heuristic to Pipeline SDF Graphs -- System Simulation of Memristor Based Computation in Memory Platforms -- Compiler Optimizations for Safe Insertion of Checkpoints in Intermittently Powered Systems -- Fine-Grained Power Modeling of Multicore Processors using FFNNs -- From High-Level Synthesis to Bundled-Data Circuits -- Energy-aware Partial-Duplication Task Mapping under Real-Time and Reliability Constraints -- A Quantitative Study of Locality in GPU Caches -- SPECIAL SESSION: Innovative Architectures for Security -- CHASM: Security Evaluation of Cache Mapping Schemes -- DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks -- Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks -- S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX -- Risk and Architecture factors in Digital Exposure Notification -- SPECIAL SESSION: European Projects on Embedded and High Performance Computing for Health Applications -- Introduction to the Special Session on "European Projects on Embedded and High Performance Computing for Health Applications" -- VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning applications -- Decision Support Systems to Promote Health and Well-being of People of Working Age: the Case of the WorkingAge EU Project -- Technical Debt Management and Energy Consumption Evaluation in Implantable Medical Devices: The SDK4ED Approach -- Distributed Training on a Highly Heterogeneus HPC System. |
| Record Nr. | UNISA-996418317003316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Embedded Computer Systems: Architectures, Modeling, and Simulation : 20th International Conference, SAMOS 2020, Samos, Greece, July 5–9, 2020, Proceedings / / edited by Alex Orailoglu, Matthias Jung, Marc Reichenbach
| Embedded Computer Systems: Architectures, Modeling, and Simulation : 20th International Conference, SAMOS 2020, Samos, Greece, July 5–9, 2020, Proceedings / / edited by Alex Orailoglu, Matthias Jung, Marc Reichenbach |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XIII, 372 p. 45 illus.) |
| Disciplina | 004.16 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Software engineering Computer networks Artificial intelligence Computer System Implementation Computer Hardware Software Engineering Computer Communication Networks Artificial Intelligence |
| ISBN | 3-030-60939-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Fast Performance Estimation and Design Space Exploration of SSD Using AI Techniques -- Combining Task- and Data-level Parallelism for High-throughput CNN Inference on Embedded CPUs-GPUs MPSoCs -- AMAIX: A Generic Analytical Model for Deep Learning Accelerators -- Data Mining in System-Level Design Space Exploration of Embedded Systems -- CoPTA: Contiguous Pattern Speculating TLB Architecture -- A Fine-Granularity Image Pyramid Accelerator for Embedded Processors -- Rec2Poly: Converting Recursions to Polyhedral Optimized Loops Using an Inspector-Executor Strategy -- DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator -- Transpiling Python to Rust for Optimized Performance -- A Fast Heuristic to Pipeline SDF Graphs -- System Simulation of Memristor Based Computation in Memory Platforms -- Compiler Optimizations for Safe Insertion of Checkpoints in Intermittently Powered Systems -- Fine-Grained Power Modeling of Multicore Processors using FFNNs -- From High-Level Synthesis to Bundled-Data Circuits -- Energy-aware Partial-Duplication Task Mapping under Real-Time and Reliability Constraints -- A Quantitative Study of Locality in GPU Caches -- SPECIAL SESSION: Innovative Architectures for Security -- CHASM: Security Evaluation of Cache Mapping Schemes -- DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks -- Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks -- S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX -- Risk and Architecture factors in Digital Exposure Notification -- SPECIAL SESSION: European Projects on Embedded and High Performance Computing for Health Applications -- Introduction to the Special Session on "European Projects on Embedded and High Performance Computing for Health Applications" -- VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning applications -- Decision Support Systems to Promote Health and Well-being of People of Working Age: the Case of the WorkingAge EU Project -- Technical Debt Management and Energy Consumption Evaluation in Implantable Medical Devices: The SDK4ED Approach -- Distributed Training on a Highly Heterogeneus HPC System. |
| Record Nr. | UNINA-9910427706703321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded computing for high performance : design exploration and customization using high-level compilation and synthesis tools / / Joao Manuel Paiva Cardoso, Jose Gabriel de Figueiredo Coutinho, Pedro C. Diniz
| Embedded computing for high performance : design exploration and customization using high-level compilation and synthesis tools / / Joao Manuel Paiva Cardoso, Jose Gabriel de Figueiredo Coutinho, Pedro C. Diniz |
| Autore | Cardoso Joao Manuel Paiva |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Cambridge, Massachusetts : , : Morgan Kaufmann, , 2017 |
| Descrizione fisica | 1 online resource (322 pages) : illustrations |
| Disciplina | 004.16 |
| Soggetto topico |
Embedded computer systems
High performance computing |
| ISBN | 0-12-804199-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910583050303321 |
Cardoso Joao Manuel Paiva
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| Cambridge, Massachusetts : , : Morgan Kaufmann, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded Engineering Education / / edited by Roman Szewczyk, Ivan Kaštelan, Miodrag Temerinac, Moshe Barak, Vlado Sruk
| Embedded Engineering Education / / edited by Roman Szewczyk, Ivan Kaštelan, Miodrag Temerinac, Moshe Barak, Vlado Sruk |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (193 p.) |
| Disciplina | 004.16 |
| Collana | Advances in Intelligent Systems and Computing |
| Soggetto topico |
Computational intelligence
Educational technology Computational Intelligence Technology and Digital Education Educational Technology |
| ISBN | 3-319-27540-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Challenges in Embedded Engineering Education -- Unified Learning Platform for Embedded Engineering -- Exercises for Embedded Engineering -- Implementation of Advanced Historical Computer Architectures -- Methods for User Involvement in the Design of Augmented Reality Systems for Engineering Education -- Augmented Reality Interface for E2LP: Assistance in Electronic Laboratories though Augmented Reality -- E2LP Remote Laboratory: e-Learning Service for Embedded Systems Education -- Advanced Projects and Applications for Embedded Engineering on E2LP Platform -- E2LP Remote Laboratory: Introduction Course and Evaluation at Warsaw University of Technology -- Exploring Aspects of Self-Regulated Learning Among Engineering Students Learning Digital System Design in the FPGA Environment - Methodology and Findings -- Is It Possible to Increase Motivation for Study Among Sophomore Electricaland Computer Engineering Students? -- Interrupts Become Features: Using On-Sensor Intelligence for Recognition Tasks. |
| Record Nr. | UNINA-9910254246503321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.]
| Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910456081903321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.]
| Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910780761003321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded hardware / / Jack Ganssle ... [et al.]
| Embedded hardware / / Jack Ganssle ... [et al.] |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910816699103321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded media processing [[electronic resource] /] / by David Katz and Rick Gentile
| Embedded media processing [[electronic resource] /] / by David Katz and Rick Gentile |
| Autore | Katz David J |
| Pubbl/distr/stampa | Boston, : Elsevier/Newnes, c2005 |
| Descrizione fisica | 1 online resource (425 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GentileRick |
| Collana | Embedded Technology |
| Soggetto topico |
Signal processing - Digital techniques
Embedded computer systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-64264-5
9786610642649 0-08-045888-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Embedded Media Processing; Copyright page; Table of Contents; Preface; History of This Book; Chapter Overviews; Chapter 1: Embedded Media Processing; Chapter 2: Memory Systems; Chapter 3: Direct Memory Access (DMA); Chapter 4: System Resource Partitioning and Code Optimization; Chapter 5: Basics of Embedded Audio Processing; Chapter 6: Basics of Embedded Video and Image Processing; Chapter 7: Media Processing Frameworks; Chapter 8: Power Management for Embedded Systems; Chapter 9: Application Examples; Acknowledgments; Acronyms; About the Authors
What's on the (Companion website)?Chapter 1: Embedded Media Processing; Why Are You Reading This Book?; So What's All the Excitement About Embedded Multimedia Systems?; A Simplified Look at a Media Processing System; Core Processing; Input/Output Subsystems-Peripheral Interfaces; Subsystem Control; Storage; Connectivity; Data Movement; Memory Subsystem; Laying the Groundwork for an EMP Application; What Kind(s) of Media Am I Dealing With?; What Do I Need to Do With the Data?; Are My System Needs Likely to Change Over Time, or Will This Be a Static System?; Is This a Portable Application? Does my Application Require a Fixed-Point or Floating-Point Device?How Does the Data Get Into and/or Out of the Chip?; How Do I Develop on the Processor?; Do I Need an Operating System?; What Are the Different Ways to Benchmark a Processor?; How Much Am I Willing to Spend?; OK, So What Processor Choices Do I Have?; A Look Inside the Blackfin Processor; System View; Computational Units; Memory Model; DMA; Instruction Flow; Event Handler; Protection of Resources; Programming Model; Power Management; What's Next?; Chapter 2: Memory Systems; Introduction; Memory Spaces; L1 Instruction Memory L1 Data MemoryCache Overview; What Is Cache?; More Cache Details; External Memory; Synchronous Memory; Asynchronous Memory; What's Next?; Chapter 3: Direct Memory Access; Introduction; DMA Controller Overview; More on the DMA Controller; Programming the DMA Controller; DMA Classifications; Advanced DMA Features; System Performance Tuning; External DMA; What's Next?; Chapter 4: System Resource Partitioning and Code Optimization; Introduction; Event Generation and Handling; System Interrupts; Programming Methodology; Architectural Features for Efficient Programming Multiple Operations per CycleHardware Loop Constructs; Specialized Addressing Modes; Interlocked Instruction Pipelines; Compiler Considerations for Efficient Programming; System and Core Synchronization; Load/Store Synchronization; Ordering; Atomic Operations; Memory Architecture-The Need for Management; Memory Access Tradeoffs; Instruction Memory Management-To Cache or To DMA?; Data Memory Management; System Guidelines for Choosing Between DMA and Cache; Memory Management Unit (MMU); Physics of Data Movement; 1. Grouping Like Transfers to Minimize Memory Bus Turnarounds; Example 4.4 2. Understanding Core and DMA SDRAM Accesses |
| Record Nr. | UNINA-9910457323303321 |
|
Katz David J
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| Boston, : Elsevier/Newnes, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded media processing [[electronic resource] /] / by David Katz and Rick Gentile
| Embedded media processing [[electronic resource] /] / by David Katz and Rick Gentile |
| Autore | Katz David J |
| Pubbl/distr/stampa | Boston, : Elsevier/Newnes, c2005 |
| Descrizione fisica | 1 online resource (425 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GentileRick |
| Collana | Embedded Technology |
| Soggetto topico |
Signal processing - Digital techniques
Embedded computer systems |
| ISBN |
1-280-64264-5
9786610642649 0-08-045888-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Embedded Media Processing; Copyright page; Table of Contents; Preface; History of This Book; Chapter Overviews; Chapter 1: Embedded Media Processing; Chapter 2: Memory Systems; Chapter 3: Direct Memory Access (DMA); Chapter 4: System Resource Partitioning and Code Optimization; Chapter 5: Basics of Embedded Audio Processing; Chapter 6: Basics of Embedded Video and Image Processing; Chapter 7: Media Processing Frameworks; Chapter 8: Power Management for Embedded Systems; Chapter 9: Application Examples; Acknowledgments; Acronyms; About the Authors
What's on the (Companion website)?Chapter 1: Embedded Media Processing; Why Are You Reading This Book?; So What's All the Excitement About Embedded Multimedia Systems?; A Simplified Look at a Media Processing System; Core Processing; Input/Output Subsystems-Peripheral Interfaces; Subsystem Control; Storage; Connectivity; Data Movement; Memory Subsystem; Laying the Groundwork for an EMP Application; What Kind(s) of Media Am I Dealing With?; What Do I Need to Do With the Data?; Are My System Needs Likely to Change Over Time, or Will This Be a Static System?; Is This a Portable Application? Does my Application Require a Fixed-Point or Floating-Point Device?How Does the Data Get Into and/or Out of the Chip?; How Do I Develop on the Processor?; Do I Need an Operating System?; What Are the Different Ways to Benchmark a Processor?; How Much Am I Willing to Spend?; OK, So What Processor Choices Do I Have?; A Look Inside the Blackfin Processor; System View; Computational Units; Memory Model; DMA; Instruction Flow; Event Handler; Protection of Resources; Programming Model; Power Management; What's Next?; Chapter 2: Memory Systems; Introduction; Memory Spaces; L1 Instruction Memory L1 Data MemoryCache Overview; What Is Cache?; More Cache Details; External Memory; Synchronous Memory; Asynchronous Memory; What's Next?; Chapter 3: Direct Memory Access; Introduction; DMA Controller Overview; More on the DMA Controller; Programming the DMA Controller; DMA Classifications; Advanced DMA Features; System Performance Tuning; External DMA; What's Next?; Chapter 4: System Resource Partitioning and Code Optimization; Introduction; Event Generation and Handling; System Interrupts; Programming Methodology; Architectural Features for Efficient Programming Multiple Operations per CycleHardware Loop Constructs; Specialized Addressing Modes; Interlocked Instruction Pipelines; Compiler Considerations for Efficient Programming; System and Core Synchronization; Load/Store Synchronization; Ordering; Atomic Operations; Memory Architecture-The Need for Management; Memory Access Tradeoffs; Instruction Memory Management-To Cache or To DMA?; Data Memory Management; System Guidelines for Choosing Between DMA and Cache; Memory Management Unit (MMU); Physics of Data Movement; 1. Grouping Like Transfers to Minimize Memory Bus Turnarounds; Example 4.4 2. Understanding Core and DMA SDRAM Accesses |
| Record Nr. | UNINA-9910784365503321 |
|
Katz David J
|
||
| Boston, : Elsevier/Newnes, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded media processing / / by David Katz and Rick Gentile
| Embedded media processing / / by David Katz and Rick Gentile |
| Autore | Katz David J |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Boston, : Elsevier/Newnes, c2005 |
| Descrizione fisica | 1 online resource (425 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GentileRick |
| Collana | Embedded Technology |
| Soggetto topico |
Signal processing - Digital techniques
Embedded computer systems |
| ISBN |
1-280-64264-5
9786610642649 0-08-045888-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Embedded Media Processing; Copyright page; Table of Contents; Preface; History of This Book; Chapter Overviews; Chapter 1: Embedded Media Processing; Chapter 2: Memory Systems; Chapter 3: Direct Memory Access (DMA); Chapter 4: System Resource Partitioning and Code Optimization; Chapter 5: Basics of Embedded Audio Processing; Chapter 6: Basics of Embedded Video and Image Processing; Chapter 7: Media Processing Frameworks; Chapter 8: Power Management for Embedded Systems; Chapter 9: Application Examples; Acknowledgments; Acronyms; About the Authors
What's on the (Companion website)?Chapter 1: Embedded Media Processing; Why Are You Reading This Book?; So What's All the Excitement About Embedded Multimedia Systems?; A Simplified Look at a Media Processing System; Core Processing; Input/Output Subsystems-Peripheral Interfaces; Subsystem Control; Storage; Connectivity; Data Movement; Memory Subsystem; Laying the Groundwork for an EMP Application; What Kind(s) of Media Am I Dealing With?; What Do I Need to Do With the Data?; Are My System Needs Likely to Change Over Time, or Will This Be a Static System?; Is This a Portable Application? Does my Application Require a Fixed-Point or Floating-Point Device?How Does the Data Get Into and/or Out of the Chip?; How Do I Develop on the Processor?; Do I Need an Operating System?; What Are the Different Ways to Benchmark a Processor?; How Much Am I Willing to Spend?; OK, So What Processor Choices Do I Have?; A Look Inside the Blackfin Processor; System View; Computational Units; Memory Model; DMA; Instruction Flow; Event Handler; Protection of Resources; Programming Model; Power Management; What's Next?; Chapter 2: Memory Systems; Introduction; Memory Spaces; L1 Instruction Memory L1 Data MemoryCache Overview; What Is Cache?; More Cache Details; External Memory; Synchronous Memory; Asynchronous Memory; What's Next?; Chapter 3: Direct Memory Access; Introduction; DMA Controller Overview; More on the DMA Controller; Programming the DMA Controller; DMA Classifications; Advanced DMA Features; System Performance Tuning; External DMA; What's Next?; Chapter 4: System Resource Partitioning and Code Optimization; Introduction; Event Generation and Handling; System Interrupts; Programming Methodology; Architectural Features for Efficient Programming Multiple Operations per CycleHardware Loop Constructs; Specialized Addressing Modes; Interlocked Instruction Pipelines; Compiler Considerations for Efficient Programming; System and Core Synchronization; Load/Store Synchronization; Ordering; Atomic Operations; Memory Architecture-The Need for Management; Memory Access Tradeoffs; Instruction Memory Management-To Cache or To DMA?; Data Memory Management; System Guidelines for Choosing Between DMA and Cache; Memory Management Unit (MMU); Physics of Data Movement; 1. Grouping Like Transfers to Minimize Memory Bus Turnarounds; Example 4.4 2. Understanding Core and DMA SDRAM Accesses |
| Record Nr. | UNINA-9910823744303321 |
|
Katz David J
|
||
| Boston, : Elsevier/Newnes, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
