Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2005
Descrizione fisica	1 online resource (vi, 194 pages) : illustrations
Disciplina	004
Soggetto topico	Information technology
ISBN	1-5090-9899-2
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Manufacturing of low-cost enzymatic biosensors using thick film processing,"Min-Chieh -- Parallel embedded systems: optimizations and challenges,"E. -- Development of nanotechnology for biomedical applications,"Ching-Jen -- Utility of high dimensional genomic composite biomarkers in therapeutic and/or diagnostic development,"S. -- SoC IP design for multimedia and communications,"M. -- Wireless strain sensing microsystem,"D. -- Advances in carbon nanotube electronics,"Yu-Ming -- Quantum dot devices for optoelectronics applications,"Y. -- Biomechanics at the micro scale,"W. -- On three-stage interconnection networks for group communications,"Hongbing -- High-precision frequency synthesizers for UWB applications,"Tai-Cheng -- A spread-spectrum clock generator using a capacitor multiplication technique,"Chao-Chyun -- General purpose RFICs using 0.35 um SiGe BiCMOS technology,"Chinchun -- Gene annotation and network in cancer research,"Hsueh-Fen -- Identification of RNA-binding protein residues using machine learning approaches,"Hsuan-Cheng -- Detecting homogeneity in protein sequence clusters for automatic functional annotation and noise detection,"Chien-Yu -- Study on fast rough alignment for two-stage protein structure comparison algorithm,"Chien-Kang -- On the potential of sensor-enhanced active RFIDs,"Ju-Peng -- IP datacasting and channel error handling with DVB-H,"J. -- Web information hierarchy and importance mining based on DOM information distillation,"Tseng-Yi -- KACU: k-means with hardware centroid-updating,"Wei-Chuan -- Bandwidth-efficient multicast in heterogeneous wireless networks,"De-Nian -- Enhanced luminescence by second-harmonic surface plasmon resonance,"H. -- Electroporation microchips for gene transfection,"Yu-Cheng -- Force measurement of specific antibody-antigen interactions in pH-varied liquid environments,"Shiming -- Hierarchical built-in self-test for system-on-chip design,"H. -- Accurate RTL power estimation for a security processor,"Kai-Shuang -- Placement for modern FPGAs," -- Energy-efficient cache architecture for multimedia applications,"C -- Code design and decoder implementation of low density parity check code," -- A Bayesian approach to virus-gene expression time course data," -- Bioinformatics analysis for genome design and synthetic biology," -- Approximation algorithms for the optimization problems of SNPs and haplotypes," -- A web-based protein retrieval system by matching visual similarity," -- Concurrent multiple-patterns snooping for intrusion detection systems," -- Research challenges and perspectives of voice over wireless LAN," -- An effective broadcast program generation algorithm for dependent data," -- Information fusion for self-organizing sensor networks,"Wei-Guang -- Trends and challenges with system-on-chip technology for multimedia system design," -- An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection," -- SoC infrastructure IP's," -- Multi-gigabit serial link transmitter - off-chip and on-chip," -- Quality assessment of gene expression data," -- Pharmacogenomics and variation in drug therapy," -- Liquid bead arrays meet multiplexing needs of clinical and research laboratories," -- A unified learning paradigm for large-scale personalized information management," -- Nano-technology in silicon foundries, -- High-performance fully integrated 4 GHz CMOS LC VCO in standard 0.18-/spl mu/m CMOS technology," -- Microchip electrophoresis and related technologies," -- Consensus scoring criteria in structure-based virtual screening," -- A biological data warehousing system for identifying transcriptional regulatory sites from gene expressions of microarray data, -- Constructing a SMBL-based S-system simulation platform," -- InfoTech algorithms for optimizing BioTech practice on high-throughput differential detections among symptom/syndrome-related pathogens," -- An overview of technology trends and innovation potential in recording, storing, dissemination, presentation, application and creation of knowledge," -- Advanced technology for managing XML document collection," -- Real-time event driven architecture for activity monitoring and early warning," -- Nanomaterials for optoelectronic devices," -- Photonic performance of Si nanocluster grown by laser assistance," -- Surface-tension-dominant powerless nano/micro fluidic systems,".
Record Nr.	UNINA-9910146817103321

Autore	Salem Mohamed A
Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2005
Disciplina	004
Soggetto topico	Electrical & Computer Engineering Information Technology Engineering & Applied Sciences
ISBN	1-5090-9901-8
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISA-996203244703316

Pubbl/distr/stampa	[Place of publication not identified], : IEEE Computer Society, 2005
Descrizione fisica	1 online resource (183 pages) : illustrations
Disciplina	004
Soggetto topico	Adaptive computing systems
ISBN	1-5090-9982-4
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design," -- FPGA-based customizable systolic architecture for image processing applications," -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method," -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform," -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays," -- Rapid prototyping of a self-timed ALU with FPGAs," -- FPGA implementation of a synchronous and self-timed neuroprocessor," -- On the design of two-level reconfigurable architectures," -- A secure self-reconfiguring architecture based on open-source hardware," -- Platform for intrinsic evolution of analogue neural networks," -- High quality uniform random number generation for massively parallel simulations in FPGA," -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks," -- Quartz: a framework for correct and efficient reconfigurable design," -- Design space exploration of coarse-grain reconfigurable DSPs," -- Optimizing register binding in FPGAs using simulated annealing," -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform," -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices," -- Applied VHDL training methodology, EDA framework and hardware implementation platform," -- FPGA implementation of DSVPWM modulator," -- A novel FPGA implementation of a welding control using a new bus architecture," -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3," -- VHDL core for 1024-point radix-4 FFT computation," -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation," -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)," -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences," -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC.
Record Nr.	UNISA-996218410303316

Pubbl/distr/stampa	[Place of publication not identified], : IEEE Computer Society, 2005
Descrizione fisica	1 online resource (183 pages) : illustrations
Disciplina	004
Soggetto topico	Adaptive computing systems
ISBN	1-5090-9982-4
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design," -- FPGA-based customizable systolic architecture for image processing applications," -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method," -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform," -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays," -- Rapid prototyping of a self-timed ALU with FPGAs," -- FPGA implementation of a synchronous and self-timed neuroprocessor," -- On the design of two-level reconfigurable architectures," -- A secure self-reconfiguring architecture based on open-source hardware," -- Platform for intrinsic evolution of analogue neural networks," -- High quality uniform random number generation for massively parallel simulations in FPGA," -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks," -- Quartz: a framework for correct and efficient reconfigurable design," -- Design space exploration of coarse-grain reconfigurable DSPs," -- Optimizing register binding in FPGAs using simulated annealing," -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform," -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices," -- Applied VHDL training methodology, EDA framework and hardware implementation platform," -- FPGA implementation of DSVPWM modulator," -- A novel FPGA implementation of a welding control using a new bus architecture," -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3," -- VHDL core for 1024-point radix-4 FFT computation," -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation," -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)," -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences," -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC.
Record Nr.	UNINA-9910145456903321