| Autore |
Pattavina Achille
|
| Pubbl/distr/stampa |
[Place of publication not identified], : John Wiley & Sons Incorporated, 1998
|
| Descrizione fisica |
1 online resource (423 pages)
|
| Disciplina |
621.3815372
|
| Soggetto topico |
Asynchronous transfer mode
Broadband communication systems
Communication technology
Computer network architectures
Switching theory
|
| ISBN |
1-280-55527-0
9786610555277
0-470-85251-8
0-470-84191-5
|
| Formato |
Materiale a stampa  |
| Livello bibliografico |
Monografia |
| Lingua di pubblicazione |
eng
|
| Nota di contenuto |
Preface -- Chapter 1 Broadband Integrated Services Digital Network -- 1.1. Current Networking Scenario -- 1.1.1. Communication services -- 1.1.2. Networking issues -- 1.2. The Path to Broadband Networking -- 1.2.1. Network evolution through ISDN to B-ISDN -- 1.2.2. The protocol reference model -- 1.3. Transfer Mode and Control of the B-ISDN -- 1.3.1. Asynchronous time division multiplexing -- 1.3.2. Congestion control issues -- 1.4. Synchronous Digital Transmission -- 1.4.1. SDH basic features -- 1.4.2. SDH multiplexing structure -- 1.4.3. Synchronization by pointers -- 1.4.4. Mapping of SDH elements -- 1.5. The ATM Standard -- 1.5.1. Protocol reference model -- 1.5.2. The physical layer -- 1.5.3. The ATM layer -- 1.5.4. The ATM adaptation layer -- 1.5.4.1. AAL Type 1 -- 1.5.4.2. AAL Type 2 -- 1.5.4.3. AAL Type 3/4 -- 1.5.4.4. AAL Type 5 -- 1.5.4.5. AAL payload capacity -- 1.6. References -- 1.7. Problems -- Chapter 2 Interconnection Networks -- 2.1. Basic Network Concepts -- 2.1.1. Equivalence between networks -- 2.1.2. Crossbar network based on splitters and combiners -- 2.2. Full-connection Multistage Networks -- 2.3. Partial-connection Multistage Networks -- 2.3.1. Banyan networks -- 2.3.1.1. Banyan network topologies -- 2.3.1.2. Banyan network properties -- 2.3.2. Sorting networks -- 2.3.2.1. Merging networks -- 2.3.2.2. Sorting networks -- 2.4. Proof of Merging Schemes -- 2.4.1. Odd-even merge sorting -- 2.4.2. Bitonic merge sorting -- 2.5. References -- 2.6. Problems -- Chapter 3 Rearrangeable Networks -- 3.1. Full-connection Multistage Networks -- 3.2. Partial-connection Multistage Networks -- 3.2.1. Partially self-routing PC networks -- 3.2.1.1. Horizontal extension -- 3.2.1.2. Vertical replication -- 3.2.1.3. Vertical replication with horizontal extension -- 3.2.1.4. Bounds on PC rearrangeable networks -- 3.2.2. Fully self-routing PC networks -- 3.2.3. Fully self-routing PC networks with output multiplexing -- 3.3. Bounds on the Network Cost Function -- 3.4. References -- 3.5. Problems -- Chapter 4 Non-blocking Networks -- 4.1. Full-connection Multistage Networks -- 4.1.1. Two-stage network -- 4.1.2. Three-stage network -- 4.1.3. Recursive network construction -- 4.2. Partial-connection Multistage Networks -- 4.2.1. Vertical replication -- 4.2.2. Vertical replication with horizontal extension -- 4.2.3. Link dilation -- 4.2.4. EGS networks -- 4.3. Comparison of Non-blocking Networks -- 4.4. Bounds on the Network Cost Function -- 4.5. References -- 4.6. Problems -- Chapter 5 The ATM Switch Model -- 5.1. The Switch Model -- 5.2. ATM Switch Taxonomy -- 5.3. References -- Chapter 6 ATM Switching with Minimum-Depth Blocking Networks -- 6.1. Unbuffered Networks -- 6.1.1. Crossbar and basic banyan networks -- 6.1.1.1. Basic structures -- 6.1.1.2. Performance -- 6.1.2. Enhanced banyan networks -- 6.1.2.1. Structures -- 6.1.2.2. Performance -- 6.2. Networks with a Single Plane and Internal Queueing -- 6.2.1. Input queueing -- 6.2.2. Output queueing -- 6.2.3. Shared queueing -- 6.2.4. Performance -- 6.3. Networks with Unbuffered Parallel Switching Planes -- 6.3.1. Basic architectures -- 6.3.2. Architectures with output queueing -- 6.3.2.1. Specific architectures -- 6.3.2.2. Performance -- 6.3.3. Architectures with combined input-output queueing -- 6.3.3.1. Models for performance analysis -- 6.3.3.2. Performance results -- 6.4. Additional Remarks -- 6.5. References -- 6.6. Problems -- Chapter 7 ATM Switching with Non-Blocking Single-Queueing Networks -- 7.1. Input Queueing -- 7.1.1. Basic architectures -- 7.1.1.1. The Three-Phase switch -- 7.1.1.2. The Ring-Reservation switch -- 7.1.2. Performance analysis -- 7.1.2.1. Asymptotic throughput -- 7.1.2.2. Packet delay -- 7.1.2.3. Packet loss probability -- 7.1.3. Enhanced architectures -- 7.1.3.1. Architecture with channel grouping -- 7.1.3.2. Architecture with windowing -- 7.2. Output Queueing -- 7.2.1. Basic architectures -- 7.2.2. Performance analysis -- 7.3. Shared Queueing -- 7.3.1. Basic architectures -- 7.3.2. Performance analysis -- 7.4. Performance Comparison of Different Queueings -- 7.5. Additional Remarks -- 7.6. References -- 7.7. Problems -- Chapter 8 ATM Switching with Non-Blocking Multiple-Queueing Networks -- 8.1. Combined Input-Output Queueing -- 8.1.1. Basic architectures -- 8.1.1.1. Internal queue loss -- 8.1.1.2. Internal backpressure -- 8.1.2. Performance analysis -- 8.1.2.1. Constrained output queue capacity -- 8.1.2.2. Arbitrary input and output queue capacities -- 8.1.3. Architectures with parallel switching planes -- 8.2. Combined Shared-Output Queueing -- 8.2.1. Basic architecture -- 8.2.2. Performance analysis -- 8.3. Combined Input-Shared Queueing -- 8.3.1. Basic architectures -- 8.3.2. Performance analysis -- 8.4. Comparison of Switch Capacities in Non-blocking Switches -- 8.5. Additional Remarks -- 8.6. References -- 8.7. Problems -- Chapter 9 ATM Switching with Arbitrary-Depth Blocking Networks -- 9.1. Switch Architectures Based on Deflection Routing -- 9.1.1. The Shuffleout switch -- 9.1.2. The Shuffle Self-Routing switch -- 9.1.3. The Rerouting switch -- 9.1.4. The Dual Shuffle switch -- 9.2. Switch Architectures Based on Simpler SEs -- 9.2.1. Previous Architectures with SEs -- 9.2.2. The Tandem Banyan switch -- 9.3. Architecture Enhancements -- 9.3.1. Extended routing -- 9.3.2. Interstage bridging -- 9.4. Performance Evaluation and Comparison -- 9.4.1. The Shuffleout switch -- 9.4.1.1. Network with 2 X 4 SEs -- 9.4.1.2. Network with 2 X 2 SEs -- 9.4.1.3. Network performance -- 9.4.2. The Shuffle Self-Routing switch -- 9.4.2.1. Basic network with 2 X 4 SEs -- 9.4.2.2. Basic network with 2 X 2 SEs -- 9.4.2.3. Basic network performance -- 9.4.2.4. Network with extended routing and 2 X 4 SEs -- 9.4.2.5. Network with extended routing and 2 X 2 SEs -- 9.4.2.6. Network performance with extended routing -- 9.4.3. The Rerouting switch -- 9.4.4. The Dual Shuffle switch -- 9.4.5. The Tandem Banyan switch -- 9.4.6. Interconnection network performance comparison -- 9.4.7. Overall switch performance -- 9.5. Switch Architectures with Parallel Switching Planes -- 9.6. Additional Remarks -- 9.7. References -- 9.8. Problems -- Appendix Synchronous Queues -- A.1 Synchronous Single-server Queues -- A.1.1. The M/D/I queue -- A.1.1.1. The asynchronous M/G/1 queue -- A.1.1.2. The asynchronous M/D/1 queue -- A.1.1.3. The synchronous M/D/1 queue -- A.1.2. The Geom (N)/D/1 queue -- A.1.3. The Geom/G/1 queue -- A.1.4. The Geom/G/1/B queue -- A.2. Synchronous Multiple-server Queues -- A.2.1. The M/D/C queue -- A.2.2. The Geom(N)/D/C/B queue -- A.3. References -- Index.
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Internet e reti : fondamenti / Achille Pattavina
