IEEE Std 1076.1-2017 (Revision of IEEE Std 1076.1-2007): : IEEE Standard VHDL Analog and Mixed-Signal Extensions / / IEEE
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| Titolo: |
IEEE Std 1076.1-2017 (Revision of IEEE Std 1076.1-2007): : IEEE Standard VHDL Analog and Mixed-Signal Extensions / / IEEE
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| Pubblicazione: | New York, USA : , : IEEE, , 2018 |
| Descrizione fisica: | 1 online resource (672 pages) |
| Disciplina: | 621.392 |
| Soggetto topico: | VHDL (Computer hardware description language) - Standards |
| Computer hardware description languages | |
| Standards, Engineering | |
| Sommario/riassunto: | The IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems, is defined in this standard. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076-2008 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models. (Additional downloadable files are available for this standard at http://standards.ieee.org/downloads/1076/1076.1-2017/). |
| Altri titoli varianti: | IEEE Std 1076.1-2017 |
| Titolo autorizzato: | IEEE Std 1076.1-2017 (Revision of IEEE Std 1076.1-2007) |
| ISBN: | 1-5044-4267-9 |
| Formato: | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione: | Inglese |
| Record Nr.: | 9910255645303321 |
| Lo trovi qui: | Univ. Federico II |
| Opac: | Controlla la disponibilità qui |