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Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
| Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari |
| Autore | Patmaönåapaön òTi. åAr |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF (xii, 455 pages) : illustrations |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | Tripura SundariB. Bala |
| Soggetto topico |
Verilog (Computer hardware description language)
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55707-9
9786610557073 0-471-72299-5 0-471-72300-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX. |
| Record Nr. | UNISA-996213314303316 |
Patmaönåapaön òTi. åAr
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
| Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari |
| Autore | Patmaönåapaön òTi. åAr |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF (xii, 455 pages) : illustrations |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | Tripura SundariB. Bala |
| Soggetto topico |
Verilog (Computer hardware description language)
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55707-9
9786610557073 0-471-72299-5 0-471-72300-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX. |
| Record Nr. | UNINA-9910146063303321 |
|
Patmaönåapaön òTi. åAr
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
| Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari |
| Autore | Patmaönåapaön òTi. åAr |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF (xii, 455 pages) : illustrations |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | Tripura SundariB. Bala |
| Soggetto topico |
Verilog (Computer hardware description language)
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55707-9
9786610557073 0-471-72299-5 0-471-72300-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX. |
| Record Nr. | UNINA-9910830990503321 |
|
Patmaönåapaön òTi. åAr
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Differential forms in electromagnetics / / Ismo V. Lindell
| Differential forms in electromagnetics / / Ismo V. Lindell |
| Autore | Lindell Ismo V. |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF ([xv], 253 pages) : illustrations |
| Disciplina | 537/.0151 |
| Collana | IEEE Press series on electromagnetic wave theory |
| Soggetto topico |
Electromagnetism - Mathematics
Differential forms Electricity & Magnetism Physics Physical Sciences & Mathematics |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55709-5
9786610557097 0-471-72308-8 0-471-72309-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multivectors -- Dyadic algebra -- Differential forms -- Electromagnetic fields and sources -- Medium, boundary, and power conditions -- Theorems and transformations -- Electromagnetic waves. |
| Record Nr. | UNINA-9910146074703321 |
|
Lindell Ismo V.
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Differential forms in electromagnetics / / Ismo V. Lindell
| Differential forms in electromagnetics / / Ismo V. Lindell |
| Autore | Lindell Ismo V. |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF ([xv], 253 pages) : illustrations |
| Disciplina | 537/.0151 |
| Collana | IEEE Press series on electromagnetic wave theory |
| Soggetto topico |
Electromagnetism - Mathematics
Differential forms Electricity & Magnetism Physics Physical Sciences & Mathematics |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55709-5
9786610557097 0-471-72308-8 0-471-72309-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multivectors -- Dyadic algebra -- Differential forms -- Electromagnetic fields and sources -- Medium, boundary, and power conditions -- Theorems and transformations -- Electromagnetic waves. |
| Record Nr. | UNISA-996211440503316 |
|
Lindell Ismo V.
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Differential forms in electromagnetics / / Ismo V. Lindell
| Differential forms in electromagnetics / / Ismo V. Lindell |
| Autore | Lindell Ismo V. |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF ([xv], 253 pages) : illustrations |
| Disciplina | 537/.0151 |
| Collana | IEEE Press series on electromagnetic wave theory |
| Soggetto topico |
Electromagnetism - Mathematics
Differential forms Electricity & Magnetism Physics Physical Sciences & Mathematics |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55709-5
9786610557097 0-471-72308-8 0-471-72309-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multivectors -- Dyadic algebra -- Differential forms -- Electromagnetic fields and sources -- Medium, boundary, and power conditions -- Theorems and transformations -- Electromagnetic waves. |
| Record Nr. | UNINA-9910830760403321 |
|
Lindell Ismo V.
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNINA-9910145767103321 |
|
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNISA-996217426803316 |
|
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNINA-9910831056803321 |
|
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electromyography : physiology, engineering, and noninvasive applications / / edited by Roberto Merletti, Philip Parker
| Electromyography : physiology, engineering, and noninvasive applications / / edited by Roberto Merletti, Philip Parker |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley-Interscience, , c2004 |
| Descrizione fisica | 1 PDF (xxii, 494 pages) : illustrations |
| Disciplina | 616.7/407547 |
| Altri autori (Persone) |
MerlettiRoberto
ParkerPhilip (Philip A.) |
| Collana | IEEE press series on biomedical engineering |
| Soggetto topico |
Electromyography - Diagnosis
Muscles Neuromuscular diseases Nervous System Diseases Tissues Myography Electrodiagnosis Musculoskeletal System Anatomy Diagnostic Techniques and Procedures Diseases Diagnosis Analytical, Diagnostic and Therapeutic Techniques and Equipment Electromyography Neuromuscular Diseases Medicine Health & Biological Sciences Internal Medicine |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55689-7
9786610556892 0-471-67837-6 1-60119-509-5 0-471-67838-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Introduction -- Contributors -- 1 BASIC PHYSIOLOGY AND BIOPHYSICS OF EMG SIGNAL GENERATION (T. Moritani, D. Stegeman, R. Merletti) -- 1.1 Introduction -- 1.2 Basic Physiology of Motor Control and Muscle Contraction -- 1.3 Basic Electrophysiology of the Muscle Cell Membrane -- References -- 2 NEEDLE AND WIRE DETECTION TECHNIQUES (J. V. Trontelj, J. Jabre, M. Mihelin) -- 2.1 Anatomical and Physiological Background of Intramuscular Recording -- 2.2 Recording Characteristics of Needle Electrodes -- 2.3 Conventional Needle EMG -- 2.4 Special Needle Recording Techniques -- 2.5 Physical Characteristics of Needle EMG Signals -- 2.6 Recording Equipment -- References -- 3 DECOMPOSITION OF INTRAMUSCULAR EMG SIGNALS (D. W. Stashuk, D. Farina, K. Sgaard) -- 3.1 Introduction -- 3.2 Basic Steps for EMG Signal Decomposition -- 3.3 Evaluation of Performance of EMG Signal Decomposition Algorithms -- 3.4 Applications of Results of the Decomposition of an Intramuscular EMG Signal -- 3.5 Conclusions -- References -- 4 BIOPHYSICS OF THE GENERATION OF EMG SIGNALS (D. Farina, R. Merletti, D. F. Stegeman) -- 4.1 Introduction -- 4.2 EMG Signal Generation -- 4.3 Crosstalk -- 4.4 Relationships between Surface EMG Features and Developed Force -- 4.5 Conclusions -- References -- 5 DETECTION AND CONDITIONING OF THE SURFACE EMG SIGNAL (R. Merletti, H. Hermens) -- 5.1 Introduction -- 5.2 Electrodes: Their Transfer Function -- 5.3 Electrodes: Their Impedance, Noise, and dc Voltages -- 5.4 Electrode Configuration, Distance, Location -- 5.5 EMG Front-End Amplifiers -- 5.6 EMG Filters: Specifications -- 5.7 Sampling and A/D Conversion -- 5.8 European Recommendations on Electrodes and Electrode Locations -- References -- 6 SINGLE-CHANNEL TECHNIQUES FOR INFORMATION EXTRACTION FROM THE SURFACE EMG SIGNAL (E. A. Clancy, D. Farina, G. Filligoi) -- 6.1 Introduction -- 6.2 Spectral Estimation of Deterministic Signals and Stochastic Processes -- 6.3 Basic Surface EMG Signal Models -- 6.4 Surface EMG Amplitude Estimation.
6.5 Extraction of Information in Frequency Domain from Surface EMG Signals -- 6.6 Joint Analysis of EMG Spectrum and Amplitude (JASA) -- 6.7 Recurrence Quantification Analysis of Surface EMG Signals -- 6.8 Conclusions -- References -- 7 MULTI-CHANNEL TECHNIQUES FOR INFORMATION EXTRACTION FROM THE SURFACE EMG (D. Farina, R. Merletti, C. Disselhorst-Klug) -- 7.1 Introduction -- 7.2 Spatial Filtering -- 7.3 Spatial Sampling -- 7.4 Estimation of Muscle-Fiber Conduction Velocity -- 7.5 Conclusions -- References -- 8 EMG MODELING AND SIMULATION (D. F. Stegeman, R. Merletti, H. J. Hermens) -- 8.1 Introduction -- 8.2 Phenomenological Models of EMG -- 8.3 Elements of Structure-Based SEMG Models -- 8.4 Basic Assumptions -- 8.5 Elementary Sources of Bioelectric Muscle Activity -- 8.6 Fiber Membrane Activity Profiles, Their Generation, Propagation, and Extinction -- 8.7 Structure of the Motor Unit -- 8.8 Volume Conduction -- 8.9 Modeling EMG Detection Systems -- 8.10 Modeling Motor Unit Recruitment and Firing Behavior -- 8.11 Inverse Modeling -- 8.12 Modeling of Muscle Fatigue -- 8.13 Other Applications of Modeling -- 8.14 Conclusions -- References -- 9 MYOELECTRIC MANIFESTATIONS OF MUSCLE FATIGUE (R. Merletti, A. Rainoldi, D. Farina) -- 9.1 Introduction -- 9.2 Definitions and Sites of Neuromuscular Fatigue -- 9.3 Assessment of Muscle Fatigue -- 9.4 How Fatigue Is Reflected in Surface EMG Variables -- 9.5 Myoelectric Manifestations of Muscle Fatigue in Isometric Voluntary Contractions -- 9.6 Fiber Typing and Myoelectric Manifestations of Muscle Fatigue -- 9.7 Factors Affecting Surface EMG Variable -- 9.8 Repeatability of Estimates of EMG Variables and Fatigue Indexes -- 9.9 Conclusions -- References -- 10 ADVANCED SIGNAL PROCESSING TECHNIQUES (D. Zazula, S. Karlsson, C. Doncarli) -- 10.1 Introduction -- 10.2 Theoretical Background -- 10.3 Decomposition of EMG Signals -- 10.4 Applications to Monitoring Myoelectric Manifestations of Muscle Fatigue -- 10.5 Conclusions -- Acknowledgment. References -- 11 SURFACE MECHANOMYOGRAM (C. Orizio) -- 11.1 The Mechanomyogram (MMG): General Aspects during Stimulated and Voluntary Contraction -- 11.2 Detection Techniques and Sensors Comparison -- 11.3 Comparison between Different Detectors -- 11.4 Simulation -- 11.5 MMG Versus Force: Joint and Adjunct Information Content -- 11.6 MMG Versus EMG: Joint and Adjunct Information Content -- 11.7 Area of Application -- References -- 12 SURFACE EMG APPLICATIONS IN NEUROLOGY (M. J. Zwarts, D. F. Stegeman, J. G. van Dijk) -- 12.1 Introduction -- 12.2 Central Nervous System Disorders and SEMG -- 12.3 Compound Muscle Action Potential and Motor Nerve Conduction -- 12.4 CMAP Generation -- 12.5 Clinical Applications -- 12.6 Pathological Fatigue -- 12.7 New Avenues: High-Density Multichannel Recording -- 12.8 Conclusion -- References -- 13 APPLICATIONS IN ERGONOMICS (G. M. Hgg, B. Melin, R. Kadefors) -- 13.1 Historic Perspective -- 13.2 Basic Workload Concepts in Ergonomics -- 13.3 Basic Surface EMG Signal Processing -- 13.4 Load Estimation and SEMG Normalization and Calibration -- 13.5 Amplitude Data Reduction over Time -- 13.6 Electromyographic Signal Alterations Indicating Muscle Fatigue in Ergonomics -- 13.7 SEMG Biofeedback in Ergonomics -- 13.8 Surface EMG and Musculoskeletal Disorders -- 13.9 Psychological Effects on EMG -- References -- 14 APPLICATIONS IN EXERCISE PHYSIOLOGY (F. Felici) -- 14.1 Introduction -- 14.2 A Few "Tips and Trickś 15.7 Workload Assessment in Occupational Biomechanics -- 15.8 Biofeedback -- 15.9 The Linear Envelope -- 15.10 Information Enhancement through Multifactorial Analysis -- References -- 16 APPLICATIONS IN REHABILITATION MEDICINE AND RELATED FIELDS (A. Rainoldi, R. Casale, P. Hodges, G. Jull) -- 16.1 Introduction -- 16.2 Electromyography as a Tool in Back and Neck Pain -- 16.3 EMG of the Pelvic Floor: A New Challenge in Neurological Rehabilitation -- 16.4 Age-Related Effects on EMG Assessment of Muscle Physiology -- 16.5 Surface EMG and Hypobaric Hipoxia -- 16.6 Microgravity Effects on Neuromuscular System -- References -- 17 BIOFEEDBACK APPLICATIONS (J. R. Cram) -- 17.1 Introduction -- 17.2 Biofeedback Application to Impairment Syndromes -- 17.3 SEMG Biofeedback Techniques -- 17.4 Summary -- References -- 18 CONTROL OF POWERED UPPER LIMB PROSTHESES (P. A. Parker, K. B. Englehart, B. S. Hudgins) -- 18.1 Introduction -- 18.2 Myoelectric Signal as a Control Input -- 18.3 Conventional Myoelectric Control -- 18.4 Emerging MEC Strategies -- 18.5 Summary -- References -- Index. |
| Record Nr. | UNINA-9910146071103321 |
| Hoboken, New Jersey : , : Wiley-Interscience, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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