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1997 IEEE International Verilog HDL Conference : proceedings : March 31-April 3, 1997, Santa Clara, California / / sponsored by Open Verilog International
| 1997 IEEE International Verilog HDL Conference : proceedings : March 31-April 3, 1997, Santa Clara, California / / sponsored by Open Verilog International |
| Pubbl/distr/stampa | Los Alamitos, California : , : IEEE Computer Society, , 1997 |
| Descrizione fisica | 1 online resource (v, 99 pages) |
| Disciplina | 621.392 |
| Soggetto topico | Verilog (Computer hardware description language) |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204373603316 |
| Los Alamitos, California : , : IEEE Computer Society, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architectures for computer vision : from algorithm to chip with Verilog / / Hong Jeong
| Architectures for computer vision : from algorithm to chip with Verilog / / Hong Jeong |
| Autore | Jeong Hong |
| Pubbl/distr/stampa | Singapore : , : Wiley, , 2014 |
| Descrizione fisica | 1 online resource (469 p.) |
| Disciplina | 621.39 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer vision |
| ISBN |
1-118-65923-6
1-118-65919-8 1-118-65921-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Architectures for Computer Vision; Contents; About the Author; Preface; Part One Verilog HDL; 1 Introduction; 1.1 Computer Architectures for Vision; 1.2 Algorithms for Computer Vision; 1.3 Computing Devices for Vision; 1.4 Design Flow for Vision Architectures; Problems; References; 2 Verilog HDL, Communication, and Control; 2.1 The Verilog System; 2.2 Hello, World!; 2.3 Modules and Ports; 2.4 UUT and TB; 2.5 Data Types and Operations; 2.6 Assignments; 2.7 Structural-Behavioral Design Elements; 2.8 Tasks and Functions; 2.9 Syntax Summary; 2.10 Simulation-Synthesis
2.11 Verilog System Tasks and Functions2.12 Converting Vision Algorithms into Verilog HDL Codes; 2.13 Design Method for Vision Architecture; 2.14 Communication by Name Reference; 2.15 Synchronous Port Communication; 2.16 Asynchronous Port Communication; 2.17 Packing and Unpacking; 2.18 Module Control; 2.19 Procedural Block Control; Problems; References; 3 Processor, Memory, and Array; 3.1 Image Processing System; 3.2 Taxonomy of Algorithms and Architectures; 3.3 Neighborhood Processor; 3.4 BPBP Processor; 3.5 DP Processor; 3.6 Forward and Backward Processors; 3.7 Frame Buffer and Image Memory 3.8 Multidimensional Array3.9 Queue; 3.10 Stack; 3.11 Linear Systolic Array; Problems; References; 4 Verilog Vision Simulator; 4.1 Vision Simulator; 4.2 Image Format Conversion; 4.3 Line-based Vision Simulator Principle; 4.4 LVSIM Top Module; 4.5 LVSIM IO System; 4.6 LVSIM RAM and Processor; 4.7 Frame-based Vision Simulator Principle; 4.8 FVSIM Top Module; 4.9 FVSIM IO System; 4.10 FVSIM RAM and Processor; 4.11 OpenCV Interface; Problems; References; Part Two Vision Principles; 5 Energy Function; 5.1 Discrete Labeling Problem; 5.2 MRF Model; 5.3 Energy Function; 5.4 Energy Function Models 5.5 Free Energy5.6 Inference Schemes; 5.7 Learning Methods; 5.8 Structure of the Energy Function; 5.9 Basic Energy Functions; Problems; References; 6 Stereo Vision; 6.1 Camera Systems; 6.2 Camera Matrices; 6.3 Camera Calibration; 6.4 Correspondence Geometry; 6.5 Camera Geometry; 6.6 Scene Geometry; 6.7 Rectification; 6.8 Appearance Models; 6.9 Fundamental Constraints; 6.10 Segment Constraints; 6.11 Constraints in Discrete Space; 6.12 Constraints in Frequency Space; 6.13 Basic Energy Functions; Problems; References; 7 Motion and Vision Modules; 7.1 3D Motion; 7.2 Direct Motion Estimation 7.3 Structure from Optical Flow7.4 Factorization Method; 7.5 Constraints on the Data Term; 7.6 Continuity Equation; 7.7 The Prior Term; 7.8 Energy Minimization; 7.9 Binocular Motion; 7.10 Segmentation Prior; 7.11 Blur Diameter; 7.12 Blur Diameter and Disparity; 7.13 Surface Normal and Disparity; 7.14 Surface Normal and Blur Diameter; 7.15 Links between Vision Modules; Problems; References; Part Three Vision Architectures; 8 Relaxation for Energy Minimization; 8.1 Euler-Lagrange Equation of the Energy Function; 8.2 Discrete Diffusion and Biharminic Operators; 8.3 SOR Equation 8.4 Relaxation Equation |
| Record Nr. | UNINA-9910132348703321 |
Jeong Hong
|
||
| Singapore : , : Wiley, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Architectures for computer vision : from algorithm to chip with Verilog / / Hong Jeong
| Architectures for computer vision : from algorithm to chip with Verilog / / Hong Jeong |
| Autore | Jeong Hong |
| Pubbl/distr/stampa | Singapore : , : Wiley, , 2014 |
| Descrizione fisica | 1 online resource (469 p.) |
| Disciplina | 621.39 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer vision |
| ISBN |
1-118-65923-6
1-118-65919-8 1-118-65921-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Architectures for Computer Vision; Contents; About the Author; Preface; Part One Verilog HDL; 1 Introduction; 1.1 Computer Architectures for Vision; 1.2 Algorithms for Computer Vision; 1.3 Computing Devices for Vision; 1.4 Design Flow for Vision Architectures; Problems; References; 2 Verilog HDL, Communication, and Control; 2.1 The Verilog System; 2.2 Hello, World!; 2.3 Modules and Ports; 2.4 UUT and TB; 2.5 Data Types and Operations; 2.6 Assignments; 2.7 Structural-Behavioral Design Elements; 2.8 Tasks and Functions; 2.9 Syntax Summary; 2.10 Simulation-Synthesis
2.11 Verilog System Tasks and Functions2.12 Converting Vision Algorithms into Verilog HDL Codes; 2.13 Design Method for Vision Architecture; 2.14 Communication by Name Reference; 2.15 Synchronous Port Communication; 2.16 Asynchronous Port Communication; 2.17 Packing and Unpacking; 2.18 Module Control; 2.19 Procedural Block Control; Problems; References; 3 Processor, Memory, and Array; 3.1 Image Processing System; 3.2 Taxonomy of Algorithms and Architectures; 3.3 Neighborhood Processor; 3.4 BPBP Processor; 3.5 DP Processor; 3.6 Forward and Backward Processors; 3.7 Frame Buffer and Image Memory 3.8 Multidimensional Array3.9 Queue; 3.10 Stack; 3.11 Linear Systolic Array; Problems; References; 4 Verilog Vision Simulator; 4.1 Vision Simulator; 4.2 Image Format Conversion; 4.3 Line-based Vision Simulator Principle; 4.4 LVSIM Top Module; 4.5 LVSIM IO System; 4.6 LVSIM RAM and Processor; 4.7 Frame-based Vision Simulator Principle; 4.8 FVSIM Top Module; 4.9 FVSIM IO System; 4.10 FVSIM RAM and Processor; 4.11 OpenCV Interface; Problems; References; Part Two Vision Principles; 5 Energy Function; 5.1 Discrete Labeling Problem; 5.2 MRF Model; 5.3 Energy Function; 5.4 Energy Function Models 5.5 Free Energy5.6 Inference Schemes; 5.7 Learning Methods; 5.8 Structure of the Energy Function; 5.9 Basic Energy Functions; Problems; References; 6 Stereo Vision; 6.1 Camera Systems; 6.2 Camera Matrices; 6.3 Camera Calibration; 6.4 Correspondence Geometry; 6.5 Camera Geometry; 6.6 Scene Geometry; 6.7 Rectification; 6.8 Appearance Models; 6.9 Fundamental Constraints; 6.10 Segment Constraints; 6.11 Constraints in Discrete Space; 6.12 Constraints in Frequency Space; 6.13 Basic Energy Functions; Problems; References; 7 Motion and Vision Modules; 7.1 3D Motion; 7.2 Direct Motion Estimation 7.3 Structure from Optical Flow7.4 Factorization Method; 7.5 Constraints on the Data Term; 7.6 Continuity Equation; 7.7 The Prior Term; 7.8 Energy Minimization; 7.9 Binocular Motion; 7.10 Segmentation Prior; 7.11 Blur Diameter; 7.12 Blur Diameter and Disparity; 7.13 Surface Normal and Disparity; 7.14 Surface Normal and Blur Diameter; 7.15 Links between Vision Modules; Problems; References; Part Three Vision Architectures; 8 Relaxation for Energy Minimization; 8.1 Euler-Lagrange Equation of the Energy Function; 8.2 Discrete Diffusion and Biharminic Operators; 8.3 SOR Equation 8.4 Relaxation Equation |
| Record Nr. | UNINA-9910817641703321 |
|
Jeong Hong
|
||
| Singapore : , : Wiley, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ASIC design and synthesis : RTL design using Verilog / / Vaibbhav Taraate
| ASIC design and synthesis : RTL design using Verilog / / Vaibbhav Taraate |
| Autore | Taraate Vaibbhav |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (XXI, 330 p. 311 illus., 184 illus. in color.) |
| Disciplina | 621.395 |
| Soggetto topico |
Application-specific integrated circuits - Design
Verilog (Computer hardware description language) |
| ISBN | 981-334-642-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design. |
| Record Nr. | UNINA-9910483227103321 |
|
Taraate Vaibbhav
|
||
| Singapore : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers
| Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, New York : , : IEEE, , 2004 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico |
Verilog (Computer hardware description language)
VHDL (Computer hardware description language) |
| ISBN | 0-7381-4524-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 61691-4-2004 - IEC 61691-4 Ed.1 |
| Record Nr. | UNINA-9910349358303321 |
| New York, New York : , : IEEE, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers
| Behavioural languages . Part 4 Verilog hardware description language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, New York : , : IEEE, , 2004 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico |
Verilog (Computer hardware description language)
VHDL (Computer hardware description language) |
| ISBN | 0-7381-4524-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 61691-4-2004 - IEC 61691-4 Ed.1 |
| Record Nr. | UNISA-996575395803316 |
| New York, New York : , : IEEE, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Computer principles and design in Verilog HDL / / Yamin Li, Hosei University
| Computer principles and design in Verilog HDL / / Yamin Li, Hosei University |
| Autore | Li Yamin |
| Pubbl/distr/stampa | Singapore : , : Wiley : , : Tsinghua University Press, , 2015 |
| Descrizione fisica | 1 online resource (1376 p.) |
| Disciplina | 621.390285/5133 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer engineering - Data processing |
| ISBN |
1-118-84112-3
1-118-84110-7 1-118-84111-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Table of Contents; Title Page; Copyright; List of Figures; List of Tables; Preface; Chapter 1: Computer Fundamentals and Performance Evaluation; 1.1 Overview of Computer Systems; 1.2 Basic Structure of Computers; 1.3 Improving Computer Performance; 1.4 Hardware Description Languages; Exercises; Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL; 2.1 Logic Gates; 2.2 Logic Circuit Design in Verilog HDL; 2.3 CMOS Logic Gates; 2.4 Four Levels/Styles of Verilog HDL; 2.5 Combinational Circuit Design; 2.6 Sequential Circuit Design; Exercises
Chapter 3: Computer Arithmetic Algorithms and Implementations3.1 Binary Integers; 3.2 Binary Addition and Subtraction; 3.3 Binary Multiplication Algorithms; 3.4 Binary Division Algorithms; 3.5 Binary Square Root Algorithms; Exercises; Chapter 4: Instruction Set Architecture and ALU Design; 4.1 Instruction Set Architecture; 4.2 MIPS Instruction Format and Registers; 4.3 MIPS Instructions and AsmSim Tool; 4.4 ALU Design; Exercises; Chapter 5: Single-Cycle CPU Design in Verilog HDL; 5.1 The Circuits Required for Executing an Instruction; 5.2 Register File Design 5.3 Single-Cycle CPU Datapath Design5.4 Single-Cycle CPU Control Unit Design; 5.5 Test Program and Simulation Waveform; Exercises; Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL; 6.1 Exceptions and Interrupts; 6.2 Design of CPU with Exception and Interrupt Mechanism; 6.3 The CPU Exception and Interrupt Tests; Exercises; Chapter 7: Multiple-Cycle CPU Design in Verilog HDL; 7.1 Dividing Instruction Execution into Several Clock Cycles; 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes; 7.3 Multiple-Cycle CPU Control Unit Design; 7.4 Memory and Test Program ExercisesChapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL; 8.1 Pipelining; 8.2 Pipeline Hazards and Solutions; 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes; 8.4 Precise Interrupts/Exceptions in Pipelined CPU; 8.5 Design of Pipelined CPU with Precise Interrupt/Exception; Exercises; Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL; 9.1 IEEE 754 Floating-Point Data Formats; 9.2 Converting between Floating-Point Number and Integer; 9.3 Floating-Point Adder (FADD) Design; 9.4 Floating-Point Multiplier (FMUL) Design 9.5 Floating-Point Divider (FDIV) Design9.6 Floating-Point Square Root (FSQRT) Design; Exercises; Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL; 10.1 CPU/FPU Pipeline Model; 10.2 Design of Register File with Two Write Ports; 10.3 Data Dependency and Pipeline Stalls; 10.4 Pipelined CPU/FPU Design in Verilog HDL; 10.5 Memory Modules and Pipelined CPU/FPU Test; Exercises; Chapter 11: Memory Hierarchy and Virtual Memory Management; 11.1 Memory; 11.2 Cache Memory; 11.3 Virtual Memory Management and TLB Design; 11.4 Mechanism of TLB-Based MIPS Memory Management; Exercises Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL |
| Record Nr. | UNINA-9910131514203321 |
|
Li Yamin
|
||
| Singapore : , : Wiley : , : Tsinghua University Press, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Computer principles and design in Verilog HDL / / Yamin Li, Hosei University
| Computer principles and design in Verilog HDL / / Yamin Li, Hosei University |
| Autore | Li Yamin |
| Pubbl/distr/stampa | Singapore : , : Wiley : , : Tsinghua University Press, , 2015 |
| Descrizione fisica | 1 online resource (1376 p.) |
| Disciplina | 621.390285/5133 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer engineering - Data processing |
| ISBN |
1-118-84112-3
1-118-84110-7 1-118-84111-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Table of Contents; Title Page; Copyright; List of Figures; List of Tables; Preface; Chapter 1: Computer Fundamentals and Performance Evaluation; 1.1 Overview of Computer Systems; 1.2 Basic Structure of Computers; 1.3 Improving Computer Performance; 1.4 Hardware Description Languages; Exercises; Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL; 2.1 Logic Gates; 2.2 Logic Circuit Design in Verilog HDL; 2.3 CMOS Logic Gates; 2.4 Four Levels/Styles of Verilog HDL; 2.5 Combinational Circuit Design; 2.6 Sequential Circuit Design; Exercises
Chapter 3: Computer Arithmetic Algorithms and Implementations3.1 Binary Integers; 3.2 Binary Addition and Subtraction; 3.3 Binary Multiplication Algorithms; 3.4 Binary Division Algorithms; 3.5 Binary Square Root Algorithms; Exercises; Chapter 4: Instruction Set Architecture and ALU Design; 4.1 Instruction Set Architecture; 4.2 MIPS Instruction Format and Registers; 4.3 MIPS Instructions and AsmSim Tool; 4.4 ALU Design; Exercises; Chapter 5: Single-Cycle CPU Design in Verilog HDL; 5.1 The Circuits Required for Executing an Instruction; 5.2 Register File Design 5.3 Single-Cycle CPU Datapath Design5.4 Single-Cycle CPU Control Unit Design; 5.5 Test Program and Simulation Waveform; Exercises; Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL; 6.1 Exceptions and Interrupts; 6.2 Design of CPU with Exception and Interrupt Mechanism; 6.3 The CPU Exception and Interrupt Tests; Exercises; Chapter 7: Multiple-Cycle CPU Design in Verilog HDL; 7.1 Dividing Instruction Execution into Several Clock Cycles; 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes; 7.3 Multiple-Cycle CPU Control Unit Design; 7.4 Memory and Test Program ExercisesChapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL; 8.1 Pipelining; 8.2 Pipeline Hazards and Solutions; 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes; 8.4 Precise Interrupts/Exceptions in Pipelined CPU; 8.5 Design of Pipelined CPU with Precise Interrupt/Exception; Exercises; Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL; 9.1 IEEE 754 Floating-Point Data Formats; 9.2 Converting between Floating-Point Number and Integer; 9.3 Floating-Point Adder (FADD) Design; 9.4 Floating-Point Multiplier (FMUL) Design 9.5 Floating-Point Divider (FDIV) Design9.6 Floating-Point Square Root (FSQRT) Design; Exercises; Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL; 10.1 CPU/FPU Pipeline Model; 10.2 Design of Register File with Two Write Ports; 10.3 Data Dependency and Pipeline Stalls; 10.4 Pipelined CPU/FPU Design in Verilog HDL; 10.5 Memory Modules and Pipelined CPU/FPU Test; Exercises; Chapter 11: Memory Hierarchy and Virtual Memory Management; 11.1 Memory; 11.2 Cache Memory; 11.3 Virtual Memory Management and TLB Design; 11.4 Mechanism of TLB-Based MIPS Memory Management; Exercises Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL |
| Record Nr. | UNINA-9910826876703321 |
|
Li Yamin
|
||
| Singapore : , : Wiley : , : Tsinghua University Press, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
| Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari |
| Autore | Patmaönåapaön òTi. åAr |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF (xii, 455 pages) : illustrations |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | Tripura SundariB. Bala |
| Soggetto topico |
Verilog (Computer hardware description language)
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55707-9
9786610557073 0-471-72299-5 0-471-72300-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX. |
| Record Nr. | UNISA-996213314303316 |
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Patmaönåapaön òTi. åAr
|
||
| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
| Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari |
| Autore | Patmaönåapaön òTi. åAr |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE Press, , c2004 |
| Descrizione fisica | 1 PDF (xii, 455 pages) : illustrations |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | Tripura SundariB. Bala |
| Soggetto topico |
Verilog (Computer hardware description language)
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-55707-9
9786610557073 0-471-72299-5 0-471-72300-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX. |
| Record Nr. | UNINA-9910146063303321 |
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| Piscataway, New Jersey : , : IEEE Press, , c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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