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Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNINA-9910145767103321 |
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNISA-996217426803316 |
|
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.]
| Digital system clocking : high performance and low-power aspects / / Vojin G. Oklobdzija ... [et al.] |
| Autore | Oklobdzija Vojin |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York : , : IEEE, , c2003 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.39 |
| Altri autori (Persone) | OklobdzijaVojin G |
| Soggetto topico |
Timing circuits - Design and construction
Memory management (Computer science) Low voltage integrated circuits - Design and construction High performance computing Electronic digital computers - Power supply Electric power - Conservation |
| Soggetto non controllato | Electrical and Electronics Engineering |
| ISBN |
1-280-25290-1
9786610252909 0-470-34300-1 0-471-72368-1 0-471-72370-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- Introduction. -- Theory of Clocked Storage Elements. -- Timing and Energy Parameters. -- Pipelining and Timing Analysis. -- High-Performance System Issues. -- Low-Energy System Issues. -- Simulation Techniques. -- State-of-the-Art Clocked Storage Elements in CMOS Technology. -- Microprocesor Examples. -- References. -- Index. |
| Record Nr. | UNINA-9910831056803321 |
|
Oklobdzija Vojin
|
||
| New York : , : IEEE, , c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment
| Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment |
| Autore | Kinniment D. J (David John) |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : J. Wiley & Sons, 2007 |
| Descrizione fisica | 1 online resource (282 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Timing circuits - Design and construction
Digital integrated circuits - Design and construction Synchronization |
| ISBN |
1-281-31822-1
9786611318222 0-470-51714-X 0-470-51713-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Synchronization and Arbitration in Digital Systems; Contents; Preface; List of Contributors; Acknowledgements; 1 Synchronization, Arbitration and Choice; 1.1 INTRODUCTION; 1.2 THE PROBLEM OF CHOICE; 1.3 CHOICE IN ELECTRONICS; 1.4 ARBITRATION; 1.5 CONTINUOUS AND DISCRETE QUANTITIES; 1.6 TIMING; 1.7 BOOK STRUCTURE; Part I; 2 Modelling Metastability; 2.1 THE SYNCHRONIZER; 2.2 LATCH MODEL; 2.3 FAILURE RATES; 2.3.1 Event Histograms and MTBF; 2.4 LATCHES AND FLIP-FLOPS; 2.5 CLOCK BACK EDGE; 3 Circuits; 3.1 LATCHES AND METASTABILITY FILTERS; 3.2 EFFECTS OF FILTERING; 3.3 THE JAMB LATCH
3.3.1 Jamb Latch Flip-. op3.4 LOW COUPLING LATCH; 3.5 THE Q-FLOP; 3.6 THE MUTEX; 3.7 ROBUST SYNCHRONIZER; 3.8 THE TRI-FLOP; 4 Noise and its Effects; 4.1 NOISE; 4.2 EFFECT OF NOISE ON A SYNCHRONIZER; 4.3 MALICIOUS INPUTS; 4.3.1 Synchronous Systems; 4.3.2 Asynchronous Systems; 5 Metastability Measurements; 5.1 CIRCUIT SIMULATION; 5.1.1 Time Step Control; 5.1.2 Long-term τ; 5.1.3 Using Bisection; 5.2 SYNCHRONIZER FLIP-FLOP TESTING; 5.3 RISING AND FALLING EDGES; 5.4 DELAY-BASED MEASUREMENT; 5.5 DEEP METASTABILITY; 5.6 BACK EDGE MEASUREMENT; 5.7 MEASURE AND SELECT; 5.7.1 Failure Measurement 5.7.2 Synchronizer Selection6 Conclusions Part I; Part II; 7 Synchronizers in Systems; 7.1 LATENCY AND THROUGHPUT; 7.2 FIFO SYNCHRONIZER; 7.3 AVOIDING SYNCHRONIZATION; 7.4 PREDICTIVE SYNCHRONIZERS; 7.5 OTHER LOW-LATENCY SYNCHRONIZERS; 7.5.1 Locally Delayed Latching (LDL); 7.5.2 Speculative Synchronization; 7.5.2.1 Synchronization error detection; 7.5.2.2 Pipelining; 7.5.2.3 Recovery; 7.6 ASYNCHRONOUS COMMUNICATION MECHANISMS (ACM); 7.6.1 Slot Mechanisms; 7.6.2 Three-slot Mechanism; 7.6.3 Four-slot Mechanism; 7.6.4 Hardware Design and Metastability; 7.7 SOME COMMON SYNCHRONIZER DESIGN ISSUES 7.7.1 Unsynchronized Paths7.7.1.1 No acknowledge; 7.7.1.2 Unsynchronized reset back edge; 7.7.2 Moving Metastability Out of Sight; 7.7.2.1 Disturbing a metastable latch; 7.7.2.2 The second chance; 7.7.2.3 Metastability blocker; 7.7.3 Multiple Synchronizer Flops; 7.7.3.1 The data synchronizer; 7.7.3.2 The redundant synchronizer; 8 Networks and Interconnects; 8.1 COMMUNICATION ON CHIP; 8.1.1 Comparison of Network Architectures; 8.2 INTERCONNECT LINKS; 8.3 SERIAL LINKS; 8.3.1 Using One Line; 8.3.2 Using Two Lines; 8.4 DIFFERENTIAL SIGNALLING; 8.5 PARALLEL LINKS; 8.5.1 One Hot Codes 8.5.2 Transition Signalling8.5.3 n of m Codes; 8.5.4 Phase Encoding; 8.5.4.1 Phase encoding sender; 8.5.4.2 Receiver; 8.5.5 Time Encoding; 8.6 PARALLEL SERIAL LINKS; 9 Pausible and Stoppable Clocks in GALS; 9.1 GALS CLOCK GENERATORS; 9.2 CLOCK TREE DELAYS; 9.3 A GALS WRAPPER; 10 Conclusions Part II; Part III; 11 Arbitration; 11.1 INTRODUCTION; 11.2 ARBITER DEFINITION; 11.3 ARBITER APPLICATIONS, RESOURCE ALLOCATION POLICIES AND COMMON ARCHITECTURES; 11.4 SIGNAL TRANSITION GRAPHS, OUR MAIN MODELLING LANGUAGE; 12 Simple Two-way Arbiters; 12.1 BASIC CONCEPTS AND CONVENTIONS 12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols |
| Record Nr. | UNINA-9910145563703321 |
|
Kinniment D. J (David John)
|
||
| Hoboken, NJ, : J. Wiley & Sons, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment
| Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment |
| Autore | Kinniment D. J (David John) |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : J. Wiley & Sons, 2007 |
| Descrizione fisica | 1 online resource (282 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Timing circuits - Design and construction
Digital integrated circuits - Design and construction Synchronization |
| ISBN |
1-281-31822-1
9786611318222 0-470-51714-X 0-470-51713-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Synchronization and Arbitration in Digital Systems; Contents; Preface; List of Contributors; Acknowledgements; 1 Synchronization, Arbitration and Choice; 1.1 INTRODUCTION; 1.2 THE PROBLEM OF CHOICE; 1.3 CHOICE IN ELECTRONICS; 1.4 ARBITRATION; 1.5 CONTINUOUS AND DISCRETE QUANTITIES; 1.6 TIMING; 1.7 BOOK STRUCTURE; Part I; 2 Modelling Metastability; 2.1 THE SYNCHRONIZER; 2.2 LATCH MODEL; 2.3 FAILURE RATES; 2.3.1 Event Histograms and MTBF; 2.4 LATCHES AND FLIP-FLOPS; 2.5 CLOCK BACK EDGE; 3 Circuits; 3.1 LATCHES AND METASTABILITY FILTERS; 3.2 EFFECTS OF FILTERING; 3.3 THE JAMB LATCH
3.3.1 Jamb Latch Flip-. op3.4 LOW COUPLING LATCH; 3.5 THE Q-FLOP; 3.6 THE MUTEX; 3.7 ROBUST SYNCHRONIZER; 3.8 THE TRI-FLOP; 4 Noise and its Effects; 4.1 NOISE; 4.2 EFFECT OF NOISE ON A SYNCHRONIZER; 4.3 MALICIOUS INPUTS; 4.3.1 Synchronous Systems; 4.3.2 Asynchronous Systems; 5 Metastability Measurements; 5.1 CIRCUIT SIMULATION; 5.1.1 Time Step Control; 5.1.2 Long-term τ; 5.1.3 Using Bisection; 5.2 SYNCHRONIZER FLIP-FLOP TESTING; 5.3 RISING AND FALLING EDGES; 5.4 DELAY-BASED MEASUREMENT; 5.5 DEEP METASTABILITY; 5.6 BACK EDGE MEASUREMENT; 5.7 MEASURE AND SELECT; 5.7.1 Failure Measurement 5.7.2 Synchronizer Selection6 Conclusions Part I; Part II; 7 Synchronizers in Systems; 7.1 LATENCY AND THROUGHPUT; 7.2 FIFO SYNCHRONIZER; 7.3 AVOIDING SYNCHRONIZATION; 7.4 PREDICTIVE SYNCHRONIZERS; 7.5 OTHER LOW-LATENCY SYNCHRONIZERS; 7.5.1 Locally Delayed Latching (LDL); 7.5.2 Speculative Synchronization; 7.5.2.1 Synchronization error detection; 7.5.2.2 Pipelining; 7.5.2.3 Recovery; 7.6 ASYNCHRONOUS COMMUNICATION MECHANISMS (ACM); 7.6.1 Slot Mechanisms; 7.6.2 Three-slot Mechanism; 7.6.3 Four-slot Mechanism; 7.6.4 Hardware Design and Metastability; 7.7 SOME COMMON SYNCHRONIZER DESIGN ISSUES 7.7.1 Unsynchronized Paths7.7.1.1 No acknowledge; 7.7.1.2 Unsynchronized reset back edge; 7.7.2 Moving Metastability Out of Sight; 7.7.2.1 Disturbing a metastable latch; 7.7.2.2 The second chance; 7.7.2.3 Metastability blocker; 7.7.3 Multiple Synchronizer Flops; 7.7.3.1 The data synchronizer; 7.7.3.2 The redundant synchronizer; 8 Networks and Interconnects; 8.1 COMMUNICATION ON CHIP; 8.1.1 Comparison of Network Architectures; 8.2 INTERCONNECT LINKS; 8.3 SERIAL LINKS; 8.3.1 Using One Line; 8.3.2 Using Two Lines; 8.4 DIFFERENTIAL SIGNALLING; 8.5 PARALLEL LINKS; 8.5.1 One Hot Codes 8.5.2 Transition Signalling8.5.3 n of m Codes; 8.5.4 Phase Encoding; 8.5.4.1 Phase encoding sender; 8.5.4.2 Receiver; 8.5.5 Time Encoding; 8.6 PARALLEL SERIAL LINKS; 9 Pausible and Stoppable Clocks in GALS; 9.1 GALS CLOCK GENERATORS; 9.2 CLOCK TREE DELAYS; 9.3 A GALS WRAPPER; 10 Conclusions Part II; Part III; 11 Arbitration; 11.1 INTRODUCTION; 11.2 ARBITER DEFINITION; 11.3 ARBITER APPLICATIONS, RESOURCE ALLOCATION POLICIES AND COMMON ARCHITECTURES; 11.4 SIGNAL TRANSITION GRAPHS, OUR MAIN MODELLING LANGUAGE; 12 Simple Two-way Arbiters; 12.1 BASIC CONCEPTS AND CONVENTIONS 12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols |
| Record Nr. | UNINA-9910819145403321 |
|
Kinniment D. J (David John)
|
||
| Hoboken, NJ, : J. Wiley & Sons, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Synchronization techniques for digital receivers / Umberto Mengali and Aldo N. D'Andrea
| Synchronization techniques for digital receivers / Umberto Mengali and Aldo N. D'Andrea |
| Autore | Mengali, Umberto |
| Pubbl/distr/stampa | New York, London : Plenum Press, c1997 |
| Descrizione fisica | xiii, 520 p. : ill. ; 24 cm |
| Disciplina | 621.382 |
| Altri autori (Persone) | D'Andrea, Aldo N. |
| Collana | Applications of communications theory |
| Soggetto topico |
Digital communications - Equipment and supplies
Timing circuits - Design and construction Synchronization |
| ISBN | 0306457253 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991001609519707536 |
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Mengali, Umberto
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| New York, London : Plenum Press, c1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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