Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Constraining designs for synthesis and timing analysis : a practical guide to synopsys design constraints (SDC) / / Sridhar Gangadharan, Sanjay Churiwala
| Constraining designs for synthesis and timing analysis : a practical guide to synopsys design constraints (SDC) / / Sridhar Gangadharan, Sanjay Churiwala |
| Autore | Gangadharan Sridhar |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, : Springer, c2013 |
| Descrizione fisica | 1 online resource (245 p.) |
| Disciplina |
004.1
620 621.381 621.3815 |
| Altri autori (Persone) | ChuriwalaSanjay |
| Soggetto topico |
Timing circuits
Time measurements |
| ISBN | 1-4614-3269-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. |
| Record Nr. | UNINA-9910438056903321 |
Gangadharan Sridhar
|
||
| New York, : Springer, c2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE
| Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE |
| Edizione | [IEC 61523-3 First edition 2004-09 IEEE 1497.] |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 2004 |
| Descrizione fisica | 1 online resource (14 pages) |
| Disciplina | 629.83 |
| Collana | IEEE Std 1497(TM)-2001 |
| Soggetto topico |
Automatic timers
Timing circuits Electric standards |
| ISBN | 0-7381-4522-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
61523-3-2004 - IEC 61523-3 Ed.1
IEC 61523-3 First edition 2004-09; IEEE 1497 IEC 61523-3 Ed.1 |
| Record Nr. | UNINA-9910137502503321 |
| Piscataway, NJ : , : IEEE, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE
| Delay and Power Calculation Standards . Part 3, Standard Delay Format (SDF) for the Electronic Design Process / / IEEE |
| Edizione | [IEC 61523-3 First edition 2004-09 IEEE 1497.] |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 2004 |
| Descrizione fisica | 1 online resource (14 pages) |
| Disciplina | 629.83 |
| Collana | IEEE Std 1497(TM)-2001 |
| Soggetto topico |
Automatic timers
Timing circuits Electric standards |
| ISBN | 0-7381-4522-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
61523-3-2004 - IEC 61523-3 Ed.1
IEC 61523-3 First edition 2004-09; IEEE 1497 IEC 61523-3 Ed.1 |
| Record Nr. | UNISA-996279339503316 |
| Piscataway, NJ : , : IEEE, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Multi-objective optimization in physical synthesis of integrated circuits / / David A. Papa, Igor L. Markov
| Multi-objective optimization in physical synthesis of integrated circuits / / David A. Papa, Igor L. Markov |
| Autore | Papa David A |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, NY, : Springer, 2012, c2013 |
| Descrizione fisica | 1 online resource (157 p.) |
| Disciplina | 621.38173 |
| Altri autori (Persone) | MarkovIgor L <1973-> (Igor Leonidovich) |
| Collana | Lecture notes in electrical engineering |
| Soggetto topico |
Integrated circuits - Design and construction
Timing circuits |
| ISBN |
9786613924421
9781283611978 128361197X 9781461413561 1461413567 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I: Introduction and Prior Art -- Timing Closure for Multi-Million-Gate Integrated Circuits -- State of the Art in Physical Synthesis -- Part II: Local Physical Synthesis and Necessary Analysis Techniques -- Buffer Insertion during Timing-Driven Placement -- Bounded Transactional Timing Analysis -- Gate Sizing During Timing-Driven Placement -- Part III: Broadening the Scope of Circuit Transformations -- Physically-Driven Logic Restructuring -- Logic Restructuring as an Aid to Physical Retiming -- Broadening the Scope of Optimization using Partitioning -- Co-Optimization of Latches and Clock Networks -- Conclusions and Future Work. |
| Record Nr. | UNINA-9910438044903321 |
|
Papa David A
|
||
| New York, NY, : Springer, 2012, c2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nanometer frequency synthesis beyond the phase-locked loop / / Liming Xiu
| Nanometer frequency synthesis beyond the phase-locked loop / / Liming Xiu |
| Autore | Xiu Liming |
| Pubbl/distr/stampa | Hoboken [New Jersey] : , : John Wiley & Sons, , 2012 |
| Descrizione fisica | 1 online resource (340 p.) |
| Disciplina | 621.381/32 |
| Collana | IEEE Press Series on Microelectronic Systems |
| Soggetto topico |
Timing circuits
Frequency synthesizers Very high speed integrated circuits |
| ISBN |
1-280-79376-7
9786613704153 1-118-34794-3 1-118-34795-1 1-118-34792-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE xi -- 1 CLOCK SIGNAL IN ELECTRONIC SYSTEMS 1 -- 1.1 The Significance of Clock Signal 1 -- 1.2 The Characteristics of Clock Signal 5 -- 1.3 Clock Signal Driving Digital System 18 -- 1.4 Clock Signal Driving Sampling System 24 -- 1.5 Extracting Clock Signal From Data: Clock Data Recovery 30 -- 1.6 Clock Usage in System-on-Chip 32 -- 1.7 Two Fields: Clock Generation and Clock Distribution 33 -- 2 CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES 37 -- 2.1 Direct Analog Frequency Synthesis 38 -- 2.2 Direct Digital Frequency Synthesis 39 -- 2.3 Indirect Method (Phase-Locked Loop Based) 41 -- 2.4 The Shared Goal: All Cycles Have Same Length-in-Time 51 -- 3 TIME-AVERAGE-FREQUENCY 53 -- 3.1 The Scale of Level and the Scale of Time 53 -- 3.2 What Is Frequency? 54 -- 3.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency 56 -- 3.4 Time-Average-Frequency in Circuit Implementation 59 -- 3.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency 61 -- 3.6 The Need of a Theory 62 -- 3.7 The Summary: Why Do We Need Time-Average-Frequency? 63 -- 4 FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE 65 -- 4.1 The Working Principle 65 -- 4.2 The Major Challenges in the Flying-Adder Circuit 68 -- 4.3 The Circuit of Proof of Concept 74 -- 4.4 The Working Circuitry 77 -- 4.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed 87 -- 4.6 The Technique of Post Divider Fractional Bits Recovery 88 -- 4.7 Flying-Adder PLL: FAPLL 90 -- 4.8 Flying-Adder Fractional Divider 91 -- 4.9 Integer-Flying-Adder Architecture 92 -- 4.10 The Algorithm to Search Optimum Parameters 98 -- 4.11 The Construction of the Accumulator 99 -- 4.12 The Construction of the High Speed Multiplex 104 -- 4.13 Non-2's Power Flying-Adder Circuit 107 -- 4.14 Expanding VCO Frequency Range in Nanometer CMOS Processes 109 -- 4.15 Multiple Flying-Adder Synthesizers 110 -- 4.16 Flying-Adder Implementation Styles 111 -- 4.17 Simulation Approaches 112 -- 4.18 The Impact of Input Mismatch on Output Jitter 113 -- 4.19 Flying-Adder Circuit as Digital Controlled Oscillator 127 -- 4.20 Flying-Adder Terminology 128 -- 4.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence 129 -- 4.22 Time-Average-Frequency and Setup Constraint: Revisit 154 -- 4.23 Sense the Frequency Difference: The Time-Average-Frequency Way 156 -- 4.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference 157 -- 4.25 Flying-Adder for Phase (Delay) Synthesis 158 -- 4.26 Flying-Adder for Duty Cycle Control 162 -- 4.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC 163.
5 DIGITAL-TO-FREQUENCY CONVERTER 167 -- 5.1 Two Ways of Representing Information 167 -- 5.2 The Converters for Transforming Information 168 -- 5.3 The Two Cornerstones of the Digital-to-Frequency Converter 170 -- 5.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter 172 -- 5.5 Convert the Spurious Energy to Noise Energy 193 -- 5.6 Move Spurs Around 198 -- 5.7 Spread the Energy 201 -- 5.8 Performance Merits 205 -- 6 THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN 211 -- 6.1 The Clocking Challenges in Reality 211 -- 6.2 Flying-Adder and Its Three Major Application Areas 216 -- 6.3 Flying-Adder for On-chip Frequency Generation 218 -- 6.4 Flying-Adder as Adaptive Clock Generator 222 -- 6.5 Flying-Adder as On-chip VCXO 230 -- 6.6 Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation 237 -- 6.7 Flying-Adder for Frequency Synchronization in Digital Communication: A Preview 240 -- 6.8 Flying-Adder for Clock Data Recovery 242 -- 6.9 Flying-Adder DLL for Deskew 255 -- 6.10 Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL) 256 -- 6.11 Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL) 262 -- 6.12 Flying-Adder Technology for Dynamic Frequency Scaling 262 -- 6.13 Flying-Adder as 1-bit DDFS 264 -- 6.14 Flying-Adder for Spread Spectrum Clocking 265 -- 6.15 Flying-Adder for Driving Sampling System 268 -- 6.16 Flying-Adder for Non-uniform Sampling 271 -- 6.17 Flying-Adder as Digital FSK Modulator 273 -- 6.18 Flying-Adder for PWM/PFW DC-DC Power Conversion 274 -- 6.19 Integrate Clocking Chips into Processing Chips 275 -- 7 LOOKING INTO FUTURE: THE ERA OF "TIME" 279 -- 7.1 The Four Fundamental Technologies in Modern Chip Design 279 -- 7.2 "Time"-Based Analog Processing 281 -- 7.3 "Time" and Frequency: Encoding Messages Through Modulation 283 -- 7.4 Manipulate "Time": The Tools 283 -- 7.5 It Is Time to Use "Time" 284 -- APPENDICES 287 -- Appendix 4.A: The VHDL Code for Flying-Adder Synthesizer 287 -- Appendix 4.B: How Close Can It Reach an Integer? 296 -- Appendix 4.C: The Seed and Set in Integer-Flying-Adder PLL 299 -- Appendix 4.D: The Number of Carries From an XIU-Accumulator 302 -- Appendix 5.A: The Flying-Adder State Machine Model (perl) 303 -- Appendix 5.B: The Flying-Adder Waveform Generator (perl) 307 -- Appendix 5.C: The Flying-Adder Waveform Generator with Triangular Modulation (perl) 310 -- Appendix 5.D: The Flying-Adder Waveform Generator with Random Modulation (perl) 314 -- Appendix 6.A: The FA-DCXO Tangent Line and Linearity Measurement 318. INDEX 321. |
| Record Nr. | UNINA-9910141255803321 |
|
Xiu Liming
|
||
| Hoboken [New Jersey] : , : John Wiley & Sons, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nanometer frequency synthesis beyond the phase-locked loop / / Liming Xiu
| Nanometer frequency synthesis beyond the phase-locked loop / / Liming Xiu |
| Autore | Xiu Liming |
| Pubbl/distr/stampa | Hoboken [New Jersey] : , : John Wiley & Sons, , 2012 |
| Descrizione fisica | 1 online resource (340 p.) |
| Disciplina | 621.381/32 |
| Collana | IEEE Press Series on Microelectronic Systems |
| Soggetto topico |
Timing circuits
Frequency synthesizers Very high speed integrated circuits |
| ISBN |
1-280-79376-7
9786613704153 1-118-34794-3 1-118-34795-1 1-118-34792-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PREFACE xi -- 1 CLOCK SIGNAL IN ELECTRONIC SYSTEMS 1 -- 1.1 The Significance of Clock Signal 1 -- 1.2 The Characteristics of Clock Signal 5 -- 1.3 Clock Signal Driving Digital System 18 -- 1.4 Clock Signal Driving Sampling System 24 -- 1.5 Extracting Clock Signal From Data: Clock Data Recovery 30 -- 1.6 Clock Usage in System-on-Chip 32 -- 1.7 Two Fields: Clock Generation and Clock Distribution 33 -- 2 CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES 37 -- 2.1 Direct Analog Frequency Synthesis 38 -- 2.2 Direct Digital Frequency Synthesis 39 -- 2.3 Indirect Method (Phase-Locked Loop Based) 41 -- 2.4 The Shared Goal: All Cycles Have Same Length-in-Time 51 -- 3 TIME-AVERAGE-FREQUENCY 53 -- 3.1 The Scale of Level and the Scale of Time 53 -- 3.2 What Is Frequency? 54 -- 3.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency 56 -- 3.4 Time-Average-Frequency in Circuit Implementation 59 -- 3.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency 61 -- 3.6 The Need of a Theory 62 -- 3.7 The Summary: Why Do We Need Time-Average-Frequency? 63 -- 4 FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE 65 -- 4.1 The Working Principle 65 -- 4.2 The Major Challenges in the Flying-Adder Circuit 68 -- 4.3 The Circuit of Proof of Concept 74 -- 4.4 The Working Circuitry 77 -- 4.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed 87 -- 4.6 The Technique of Post Divider Fractional Bits Recovery 88 -- 4.7 Flying-Adder PLL: FAPLL 90 -- 4.8 Flying-Adder Fractional Divider 91 -- 4.9 Integer-Flying-Adder Architecture 92 -- 4.10 The Algorithm to Search Optimum Parameters 98 -- 4.11 The Construction of the Accumulator 99 -- 4.12 The Construction of the High Speed Multiplex 104 -- 4.13 Non-2's Power Flying-Adder Circuit 107 -- 4.14 Expanding VCO Frequency Range in Nanometer CMOS Processes 109 -- 4.15 Multiple Flying-Adder Synthesizers 110 -- 4.16 Flying-Adder Implementation Styles 111 -- 4.17 Simulation Approaches 112 -- 4.18 The Impact of Input Mismatch on Output Jitter 113 -- 4.19 Flying-Adder Circuit as Digital Controlled Oscillator 127 -- 4.20 Flying-Adder Terminology 128 -- 4.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence 129 -- 4.22 Time-Average-Frequency and Setup Constraint: Revisit 154 -- 4.23 Sense the Frequency Difference: The Time-Average-Frequency Way 156 -- 4.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference 157 -- 4.25 Flying-Adder for Phase (Delay) Synthesis 158 -- 4.26 Flying-Adder for Duty Cycle Control 162 -- 4.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC 163.
5 DIGITAL-TO-FREQUENCY CONVERTER 167 -- 5.1 Two Ways of Representing Information 167 -- 5.2 The Converters for Transforming Information 168 -- 5.3 The Two Cornerstones of the Digital-to-Frequency Converter 170 -- 5.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter 172 -- 5.5 Convert the Spurious Energy to Noise Energy 193 -- 5.6 Move Spurs Around 198 -- 5.7 Spread the Energy 201 -- 5.8 Performance Merits 205 -- 6 THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN 211 -- 6.1 The Clocking Challenges in Reality 211 -- 6.2 Flying-Adder and Its Three Major Application Areas 216 -- 6.3 Flying-Adder for On-chip Frequency Generation 218 -- 6.4 Flying-Adder as Adaptive Clock Generator 222 -- 6.5 Flying-Adder as On-chip VCXO 230 -- 6.6 Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation 237 -- 6.7 Flying-Adder for Frequency Synchronization in Digital Communication: A Preview 240 -- 6.8 Flying-Adder for Clock Data Recovery 242 -- 6.9 Flying-Adder DLL for Deskew 255 -- 6.10 Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL) 256 -- 6.11 Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL) 262 -- 6.12 Flying-Adder Technology for Dynamic Frequency Scaling 262 -- 6.13 Flying-Adder as 1-bit DDFS 264 -- 6.14 Flying-Adder for Spread Spectrum Clocking 265 -- 6.15 Flying-Adder for Driving Sampling System 268 -- 6.16 Flying-Adder for Non-uniform Sampling 271 -- 6.17 Flying-Adder as Digital FSK Modulator 273 -- 6.18 Flying-Adder for PWM/PFW DC-DC Power Conversion 274 -- 6.19 Integrate Clocking Chips into Processing Chips 275 -- 7 LOOKING INTO FUTURE: THE ERA OF "TIME" 279 -- 7.1 The Four Fundamental Technologies in Modern Chip Design 279 -- 7.2 "Time"-Based Analog Processing 281 -- 7.3 "Time" and Frequency: Encoding Messages Through Modulation 283 -- 7.4 Manipulate "Time": The Tools 283 -- 7.5 It Is Time to Use "Time" 284 -- APPENDICES 287 -- Appendix 4.A: The VHDL Code for Flying-Adder Synthesizer 287 -- Appendix 4.B: How Close Can It Reach an Integer? 296 -- Appendix 4.C: The Seed and Set in Integer-Flying-Adder PLL 299 -- Appendix 4.D: The Number of Carries From an XIU-Accumulator 302 -- Appendix 5.A: The Flying-Adder State Machine Model (perl) 303 -- Appendix 5.B: The Flying-Adder Waveform Generator (perl) 307 -- Appendix 5.C: The Flying-Adder Waveform Generator with Triangular Modulation (perl) 310 -- Appendix 5.D: The Flying-Adder Waveform Generator with Random Modulation (perl) 314 -- Appendix 6.A: The FA-DCXO Tangent Line and Linearity Measurement 318. INDEX 321. |
| Record Nr. | UNINA-9910820686903321 |
|
Xiu Liming
|
||
| Hoboken [New Jersey] : , : John Wiley & Sons, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
PATMOS 2018 : 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation : 2-4 July 2018, Spain / / Institute of Electrical and Electronics Engineers
| PATMOS 2018 : 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation : 2-4 July 2018, Spain / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (163 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits
Timing circuits |
| ISBN | 1-5386-6365-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996279942503316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
PATMOS 2018 : 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation : 2-4 July 2018, Spain / / Institute of Electrical and Electronics Engineers
| PATMOS 2018 : 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation : 2-4 July 2018, Spain / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (163 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits
Timing circuits |
| ISBN | 1-5386-6365-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910286358703321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synchronization in wireless sensor networks : parameter estimation, performance benchmarks and protocols / Erchin Serpedin and Qasim M. Chaudhari
| Synchronization in wireless sensor networks : parameter estimation, performance benchmarks and protocols / Erchin Serpedin and Qasim M. Chaudhari |
| Autore | Serpedin, Erchin, 1967- |
| Pubbl/distr/stampa | Cambridge, UK ; New York : Cambridge University Press, 2009 |
| Descrizione fisica | xii, 232 p. : ill. ; 26 cm |
| Disciplina | 681.2 |
| Altri autori (Persone) | Chaudhari, Qasim M. |
| Soggetto topico |
Wireless sensor networks
Synchronous data transmission systems Timing circuits |
| ISBN | 9780521764421 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991001106699707536 |
|
Serpedin, Erchin, 1967-
|
||
| Cambridge, UK ; New York : Cambridge University Press, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
Synchronization of digital telecommunications networks
| Synchronization of digital telecommunications networks |
| Autore | Bregni Stefano |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | [Place of publication not identified], : Wiley, 2002 |
| Descrizione fisica | 1 online resource (1 v.) : ill |
| Disciplina | 621.382/16 |
| Soggetto topico |
Synchronous data transmission systems
Timing circuits Synchronization Electrical & Computer Engineering Engineering & Applied Sciences Telecommunications |
| ISBN |
9786610554645
9780470845882 0470845880 9781280554643 1280554649 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9911019624703321 |
|
Bregni Stefano
|
||
| [Place of publication not identified], : Wiley, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
