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2006 1st International Conference on Nano-Networks and Workshops : Lausanne, Switzerland, 14-16 September 2006
| 2006 1st International Conference on Nano-Networks and Workshops : Lausanne, Switzerland, 14-16 September 2006 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip - Design and construction
Nanostructured materials Integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Soggetto non controllato | network on chip; - networks on chip; - NoC |
| ISBN |
1-5090-9613-2
1-4244-0391-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996211213203316 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 1st International Conference on Nano-Networks and Workshops : Lausanne, Switzerland, 14-16 September 2006
| 2006 1st International Conference on Nano-Networks and Workshops : Lausanne, Switzerland, 14-16 September 2006 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip - Design and construction
Nanostructured materials Integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Soggetto non controllato | network on chip; - networks on chip; - NoC |
| ISBN |
1-5090-9613-2
1-4244-0391-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146687303321 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Analog/RF and mixed-signal circuit systematic design / / Mourad Fakhfakh, Esteban Tlelo-Cuautle, and Rafael Castro-Lopez (eds.)
| Analog/RF and mixed-signal circuit systematic design / / Mourad Fakhfakh, Esteban Tlelo-Cuautle, and Rafael Castro-Lopez (eds.) |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Heidelberg, Germany : , : Springer, , 2013 |
| Descrizione fisica | 1 online resource (xii, 379 pages) : illustrations (some color) |
| Disciplina | 621.3815 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Systems on a chip - Design and construction Linear integrated circuits - Design and construction |
| ISBN | 3-642-36329-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Title ""; ""Foreword""; ""Preface""; ""Contents""; ""Part I Methodologies""; ""Towards Automatic Structural Analysis of Mixed-Signal Circuits""; ""Introduction""; ""Preprocessing""; ""Building Block Recognition""; ""Analog, Mixed-Signal and Digital Building Block Library""; ""Recognition Conflicts and Their Resolution""; ""Recognition Algorithm""; ""Structural Signal Flow Analysis""; ""Generation""; ""Assignment of Pass�Gate Directions""; ""Analog / Digital Partitioning""; ""Transformation to Temporal ESFG""; ""Logic Function Extraction""
""Computation of Logic Function for Building Blocks""""Computation of Overall Logic Function""; ""Application Examples""; ""Description Generation for Digital Standard Cell Libraries""; ""Structural Analysis of Mixed-Signal Circuits""; ""Conclusion""; ""References""; ""Efficient Synthesis Methods for High-Frequency Integrated Passive Components and Amplifiers""; ""Introduction""; ""Review of Related Works and Challenges""; ""RF Integrated Circuit Synthesis ""; ""Basic Computational Intelligence Techniques""; ""Differential Evolution""; ""Gaussian Process Machine Learning"" ""Naive Bayes Classifier""""MMLDE: Efficient Synthesis of Integrated Passive Components at High Frequencies""; ""Key Ideas of MMLDE""; ""Expected Improvement Prescreening""; ""The General Framework of MMLDE""; ""Experimental Results of MMLDE""; ""EMLDE: Efficient Synthesis of mm-Wave Linear Amplifiers""; ""Overview of EMLDE""; ""Key Algorithms in the EMLDE Method""; ""The Embedded SBDE Algorithm""; ""The EMLDE Method""; ""Experimental Verification of the EMLDE Method""; ""Example and Settings""; ""Example: Three-Stage Linear Amplifier Synthesis""; ""Conclusion""; ""References"" ""Self-Healing Circuits Using Statistical Element Selection""""Introduction""; ""Process Variations""; ""Systematic Variations""; ""Random Variations""; ""Mismatch Correction Methods""; ""Statistical Element Selection""; ""Basis""; ""Methodology ""; ""Comparator Array in 65nm Bulk CMOS Technology""; ""Design Architecture""; ""Testing Setup""; ""Measurement Results ""; ""An 8-bit 1.5-GHz Flash ADC in 65nm CMOS Process""; ""Flash ADC Architecture""; ""Comparator Design""; ""Measurement Results ""; ""Conclusion""; ""References"" ""Improving Design Feature Reuse in Analog Circuit Design through Topological-Symbolic Comparison and Design Concept Combination""""Introduction""; ""Related Work""; ""Circuit Synthesis Based on Concept Comparison and Combination""; ""Systematic Comparison of Analog Circuits""; ""Topological Matching""; ""Symbolic Matching""; ""Constraint Generation""; ""Performance Characterization ""; ""Experiments""; ""Conclusion""; ""References ""; ""Graph-Based Symbolic and Symbolic Sensitivity Analysis of Analog Integrated Circuits""; ""Introduction""; ""Nullor Circuit Equivalents"" ""Graph-Based Determinant Representation"" |
| Record Nr. | UNINA-9910437911603321 |
| Heidelberg, Germany : , : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Correct-by-construction approaches for SoC design / / Roopak Sinha, Parthasarathi Roop, Samik Basu
| Correct-by-construction approaches for SoC design / / Roopak Sinha, Parthasarathi Roop, Samik Basu |
| Autore | Sinha Roopak |
| Pubbl/distr/stampa | New York, : Springer Science, 2014 |
| Descrizione fisica | 1 online resource (xxi, 144 pages) : illustrations (some color) |
| Disciplina |
004.1
620 621.381 621.3815 |
| Collana | Gale eBooks |
| Soggetto topico | Systems on a chip - Design and construction |
| ISBN | 1-4614-7864-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | System-on-A-Chip Design.- The AMBA SOC Platform.- Automatic Verification using Model and Module Checking -- Models for SoCs and Specifications -- SoC Design Methodology -- Automatic Protocol Conversion -- Related Work and Outlook.- Appendix: Converter Generation Algorithm. |
| Record Nr. | UNINA-9910299738403321 |
Sinha Roopak
|
||
| New York, : Springer Science, 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby
| Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby |
| Autore | Ashby Robert |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina | 004.6 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910457074203321 |
|
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby
| Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby |
| Autore | Ashby Robert |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina | 004.6 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910784361303321 |
|
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designer's guide to the Cypress PSoC / / by Robert Ashby
| Designer's guide to the Cypress PSoC / / by Robert Ashby |
| Autore | Ashby Robert |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina |
004.6
004.16 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910815972503321 |
|
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910458596803321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910784654303321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910808929603321 |
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Leibson Steve
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| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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