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2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland
| 2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland |
| Pubbl/distr/stampa | [Place of publication not identified], : Tampere University of Technology, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996202167203316 |
| [Place of publication not identified], : Tampere University of Technology, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland
| 2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland |
| Pubbl/distr/stampa | [Place of publication not identified], : Tampere University of Technology, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872534703321 |
| [Place of publication not identified], : Tampere University of Technology, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2005 International Symposium on System-on-Chip proceedings
| 2005 International Symposium on System-on-Chip proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2005 |
| Descrizione fisica | 1 online resource (ix, 187 pages) : illustrations |
| Disciplina | 004.16 |
| Soggetto topico | Systems on a chip |
| ISBN | 1-5090-9935-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Design Methodologies and CAD Tool Flows for Networks on Chips,"S. -- Network-on-Chip: A New Paradigm for System-on-Chip Design,"J. -- System-level modeling and validation increase design productivity and save errors,"B. -- Low-Power SOC Design Using Configurable Processors-The Non-Nuclear Option,"C. -- Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip,"P. -- Instruction Folding for an Asynchronous Java Co-Processor,"T. -- Dynamic Verification of OCP-based SoC,"N. -- Reconfigurable Security Primitive for Embedded Systems,"G. -- A FPGA Implementation of An Open-Source Floating-Point Computation System,"C. -- Multiplierless Reconfigurable Processing Element And Its Applications to DSP Kernels,"SangKyu -- SOPC Builder, a Novel Design Methodology for IP Integration,"S. -- Proof of Concept for Low-power Digital Asynchronous IC Design,"T. -- Exploiting the Area X Performance Trade-off with Code Compression,"E. -- Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell Search,"K. -- Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems,"P. -- Providing Compilers and Application Program Support for Reconfigurable SoCs: Radical but Overdue,"A. -- Practical Assertion-based Formal Verification for SoC Designs,"Ping -- Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips,"M. -- Design-Time Application Exploration for MP-SoC Customized Run-Time Management,"C. -- Overview of the 4S Project,"G. -- Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures,"A. -- Run-time Mapping of Applications to a Heterogeneous SoC,"L. -- Energy Model of Networks-on-Chip and a Bus,"P. -- SoC Leakage Power Reduction Algorithm by Input Vector Control,"Xiaotao -- ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs,"M. -- Towards a Formal Power Estimation Framework for Hardware Systems,"J. -- Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration,"Jae-Gon -- An Effective IP Reuse Methodology for Quality System-on-Chip Design,"S. -- Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow,"J. -- Architectural and Physical Design Optimizations for Efficient Intra-tile Communication,"A. -- Formal Modelling of Synchronous Hardware Components for System-on-Chip,"T. -- Rapid Refinable SoC SDR Design,"P. -- Reliable Asynchronous Links for SoC,"E. -- Analysis of System Architecture of FPGA-based Embedded Controller for Magnetically Suspended Rotor,"R. -- FPGA Prototyping: Untapping Potential within the Multimillion-Gate System-on-Chip Design Space,"A. -- Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems,"M. -- A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations,"L. -- Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs,"H. -- Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time Ratio,"S. -- An On-Chip CDMA Communication Network,"Xin -- High-Level Switching Activity Prediction Through Sampled Monitored Simulation,"F. -- Exploitation of UML 2.0 - Based Platform Service Model and SystemC Workload Simulation in MPEG-4 Partitioning,"J. -- An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip,"T. -- A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip,"A. -- System-level Modeling of Wireless Integrated Sensor Networks,"K. -- Future Trends in SoC Interconnect,"S. |
| Record Nr. | UNISA-996203242203316 |
| [Place of publication not identified], : IEEE, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2005 International Symposium on System-on-Chip proceedings
| 2005 International Symposium on System-on-Chip proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2005 |
| Descrizione fisica | 1 online resource (ix, 187 pages) : illustrations |
| Disciplina | 004.16 |
| Soggetto topico | Systems on a chip |
| ISBN |
9781509099351
1509099352 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Design Methodologies and CAD Tool Flows for Networks on Chips,"S. -- Network-on-Chip: A New Paradigm for System-on-Chip Design,"J. -- System-level modeling and validation increase design productivity and save errors,"B. -- Low-Power SOC Design Using Configurable Processors-The Non-Nuclear Option,"C. -- Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip,"P. -- Instruction Folding for an Asynchronous Java Co-Processor,"T. -- Dynamic Verification of OCP-based SoC,"N. -- Reconfigurable Security Primitive for Embedded Systems,"G. -- A FPGA Implementation of An Open-Source Floating-Point Computation System,"C. -- Multiplierless Reconfigurable Processing Element And Its Applications to DSP Kernels,"SangKyu -- SOPC Builder, a Novel Design Methodology for IP Integration,"S. -- Proof of Concept for Low-power Digital Asynchronous IC Design,"T. -- Exploiting the Area X Performance Trade-off with Code Compression,"E. -- Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell Search,"K. -- Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems,"P. -- Providing Compilers and Application Program Support for Reconfigurable SoCs: Radical but Overdue,"A. -- Practical Assertion-based Formal Verification for SoC Designs,"Ping -- Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips,"M. -- Design-Time Application Exploration for MP-SoC Customized Run-Time Management,"C. -- Overview of the 4S Project,"G. -- Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures,"A. -- Run-time Mapping of Applications to a Heterogeneous SoC,"L. -- Energy Model of Networks-on-Chip and a Bus,"P. -- SoC Leakage Power Reduction Algorithm by Input Vector Control,"Xiaotao -- ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs,"M. -- Towards a Formal Power Estimation Framework for Hardware Systems,"J. -- Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration,"Jae-Gon -- An Effective IP Reuse Methodology for Quality System-on-Chip Design,"S. -- Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow,"J. -- Architectural and Physical Design Optimizations for Efficient Intra-tile Communication,"A. -- Formal Modelling of Synchronous Hardware Components for System-on-Chip,"T. -- Rapid Refinable SoC SDR Design,"P. -- Reliable Asynchronous Links for SoC,"E. -- Analysis of System Architecture of FPGA-based Embedded Controller for Magnetically Suspended Rotor,"R. -- FPGA Prototyping: Untapping Potential within the Multimillion-Gate System-on-Chip Design Space,"A. -- Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems,"M. -- A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations,"L. -- Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs,"H. -- Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time Ratio,"S. -- An On-Chip CDMA Communication Network,"Xin -- High-Level Switching Activity Prediction Through Sampled Monitored Simulation,"F. -- Exploitation of UML 2.0 - Based Platform Service Model and SystemC Workload Simulation in MPEG-4 Partitioning,"J. -- An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip,"T. -- A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip,"A. -- System-level Modeling of Wireless Integrated Sensor Networks,"K. -- Future Trends in SoC Interconnect,"S. |
| Record Nr. | UNINA-9910146818703321 |
| [Place of publication not identified], : IEEE, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2006 6th International Workshop on Systemon Chip for Real Time Applications
| 2006 6th International Workshop on Systemon Chip for Real Time Applications |
| Autore | Badawy Wael |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2006 |
| Descrizione fisica | 1 online resource (xiii, 224 pages) |
| Disciplina | 621.3950285 |
| Soggetto topico |
Application-specific integrated circuits - Design and construction
Systems on a chip |
| ISBN | 1-5090-9360-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996201760603316 |
Badawy Wael
|
||
| [Place of publication not identified], : I E E E, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 6th International Workshop on Systemon Chip for Real Time Applications
| 2006 6th International Workshop on Systemon Chip for Real Time Applications |
| Autore | Badawy Wael |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2006 |
| Descrizione fisica | 1 online resource (xiii, 224 pages) |
| Disciplina | 621.3950285 |
| Soggetto topico |
Application-specific integrated circuits - Design and construction
Systems on a chip |
| ISBN |
9781509093601
1509093605 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910143032603321 |
|
Badawy Wael
|
||
| [Place of publication not identified], : I E E E, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration, and Software : (DCAS 06) : October 29-30, 2006 : the University of Texas at Dallas, Richardson, TX / / sponsored by the Dallas Chapter/IEEE CAS, and by the IEEE Circuits and Systems Society
| 2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration, and Software : (DCAS 06) : October 29-30, 2006 : the University of Texas at Dallas, Richardson, TX / / sponsored by the Dallas Chapter/IEEE CAS, and by the IEEE Circuits and Systems Society |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Integrated circuits Electronic circuits |
| ISBN | 1-5090-9382-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software
Internet Security |
| Record Nr. | UNISA-996280902003316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration, and Software : (DCAS 06) : October 29-30, 2006 : the University of Texas at Dallas, Richardson, TX / / sponsored by the Dallas Chapter/IEEE CAS, and by the IEEE Circuits and Systems Society
| 2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration, and Software : (DCAS 06) : October 29-30, 2006 : the University of Texas at Dallas, Richardson, TX / / sponsored by the Dallas Chapter/IEEE CAS, and by the IEEE Circuits and Systems Society |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Integrated circuits Electronic circuits |
| ISBN |
9781509093823
1509093826 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software
Internet Security |
| Record Nr. | UNINA-9910143041903321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The 2006 International Conference on MEMS, NANO, and Smart Systems : December 27-29, 2006, Cairo, Egypt : proceedings
| The 2006 International Conference on MEMS, NANO, and Smart Systems : December 27-29, 2006, Cairo, Egypt : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Disciplina | 621 |
| Soggetto topico |
Microelectromechanical systems
Nanotechnology Systems on a chip Intelligent control systems Smart materials Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9427-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996201760403316 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
The 2006 International Conference on MEMS, NANO, and Smart Systems : December 27-29, 2006, Cairo, Egypt : proceedings
| The 2006 International Conference on MEMS, NANO, and Smart Systems : December 27-29, 2006, Cairo, Egypt : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Disciplina | 621 |
| Soggetto topico |
Microelectromechanical systems
Nanotechnology Systems on a chip Intelligent control systems Smart materials Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
9781509094271
150909427X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910143032503321 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
