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ESD : analog circuits and design / / Steven H Voldman
| ESD : analog circuits and design / / Steven H Voldman |
| Autore | Voldman Steven H. |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2015 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/3 |
| Collana | ESD Series |
| Soggetto topico |
Semiconductors - Protection
Analog integrated circuits - Protection Analog integrated circuits - Design and construction Electrostatics Static eliminators |
| ISBN |
1-118-70147-X
1-118-70140-2 1-118-70168-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout 2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout 2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror 3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode 4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET |
| Record Nr. | UNINA-9910132172303321 |
Voldman Steven H.
|
||
| Chichester, England : , : Wiley, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : analog circuits and design / / Steven H Voldman
| ESD : analog circuits and design / / Steven H Voldman |
| Autore | Voldman Steven H. |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2015 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/3 |
| Collana | ESD Series |
| Soggetto topico |
Semiconductors - Protection
Analog integrated circuits - Protection Analog integrated circuits - Design and construction Electrostatics Static eliminators |
| ISBN |
1-118-70147-X
1-118-70140-2 1-118-70168-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout 2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout 2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror 3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode 4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET |
| Record Nr. | UNINA-9910807232603321 |
|
Voldman Steven H.
|
||
| Chichester, England : , : Wiley, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman
| ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Record Nr. | UNINA-9910143743003321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman
| ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina |
621.384
621.38412 |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Radio frequency integrated circuits - Protection Electrostatics Electric discharges - Prevention Static eliminators |
| ISBN |
1-280-72219-3
9786610722198 0-470-06140-5 0-470-06139-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; Preface; Acknowledgements; Chapter 1 RF DESIGN and ESD; 1.1 Fundamental Concepts of ESD Design; 1.2 Fundamental Concepts of RF ESD Design; 1.3 Key RF ESD Contributions; 1.4 Key RF ESD Patents; 1.5 ESD Failure Mechanisms; 1.5.1 RF CMOS ESD Failure Mechanisms; 1.5.2 Silicon Germanium ESD Failure Mechanisms; 1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices; 1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms; 1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms; 1.5.6 RF Bipolar Circuits ESD Failure Mechanisms; 1.6 RF Basics
1.7 Two-Port Network Parameters1.7.1 Z-Parameters; 1.7.2 Y-Parameters; 1.7.3. S-Parameters; 1.7.4 T-Parameters; 1.8 Stability: RF Design Stability and ESD; 1.9 Device Degradation and ESD Failure; 1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria; 1.9.2 RF Parameters, ESD Degradation, and Failure Criteria; 1.10 RF ESD Testing; 1.10.1 ESD Testing Models; 1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology; 1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology; 1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing 1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation1.11.2 ESD Degradation System Level Method - Eye Tests; 1.12 Product Level ESD Test and RF Functional Parameter Failure; 1.13 Combined RF and ESD TLP Test Systems; 1.14 Closing Comments and Summary; Problems; References; Chapter 2 RF ESD Design; 2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows; 2.1.1 Ideal ESD Networks and the Current-Voltage d.c. Design Window; 2.1.2 Ideal ESD Networks in the Frequency Domain Design Window; 2.2 RF ESD Design Methods: Linearity 2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit2.4 RF ESD Design Methods: Method of Substitution; 2.4.1 Method of Substitution of Passive Element to ESD Network Element; 2.4.2 Substitution of ESD Network Element to Passive Element; 2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks; 2.5.1 RF ESD Method - Conversion of Matching Networks to ESD Networks; 2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks; 2.5.2.1 Conversion of ESD Networks into L-Match Networks; 2.5.2.2 Conversion of ESD Networks into Pie-Match Networks 2.5.2.3 Conversion of ESD Networks into T-Match Networks2.6 RF ESD Design Methods: Inductive Shunt; 2.7 RF ESD Design Methods: Cancellation Method; 2.7.1 Quality Factors and the Cancellation Method; 2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit; 2.7.3 Cancellation Method and ESD Circuitry; 2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator; 2.9 RF ESD Design Methods: Lumped versus Distributed Loads; 2.9.1 RF ESD Distributed Load with Coplanar Wave Guides; 2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices 2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration |
| Record Nr. | UNINA-9910830973303321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : circuits and devices / / Steven H. Voldman
| ESD : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Altri titoli varianti | Circuits and devices |
| Record Nr. | UNINA-9910824563303321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : RF technology and circuits / / Steven H. Voldman
| ESD : RF technology and circuits / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina | 621.384/12 |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Radio frequency integrated circuits - Protection Electrostatics Electric discharges - Prevention Static eliminators |
| ISBN |
1-280-72219-3
9786610722198 0-470-06140-5 0-470-06139-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; Preface; Acknowledgements; Chapter 1 RF DESIGN and ESD; 1.1 Fundamental Concepts of ESD Design; 1.2 Fundamental Concepts of RF ESD Design; 1.3 Key RF ESD Contributions; 1.4 Key RF ESD Patents; 1.5 ESD Failure Mechanisms; 1.5.1 RF CMOS ESD Failure Mechanisms; 1.5.2 Silicon Germanium ESD Failure Mechanisms; 1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices; 1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms; 1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms; 1.5.6 RF Bipolar Circuits ESD Failure Mechanisms; 1.6 RF Basics
1.7 Two-Port Network Parameters1.7.1 Z-Parameters; 1.7.2 Y-Parameters; 1.7.3. S-Parameters; 1.7.4 T-Parameters; 1.8 Stability: RF Design Stability and ESD; 1.9 Device Degradation and ESD Failure; 1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria; 1.9.2 RF Parameters, ESD Degradation, and Failure Criteria; 1.10 RF ESD Testing; 1.10.1 ESD Testing Models; 1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology; 1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology; 1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing 1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation1.11.2 ESD Degradation System Level Method - Eye Tests; 1.12 Product Level ESD Test and RF Functional Parameter Failure; 1.13 Combined RF and ESD TLP Test Systems; 1.14 Closing Comments and Summary; Problems; References; Chapter 2 RF ESD Design; 2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows; 2.1.1 Ideal ESD Networks and the Current-Voltage d.c. Design Window; 2.1.2 Ideal ESD Networks in the Frequency Domain Design Window; 2.2 RF ESD Design Methods: Linearity 2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit2.4 RF ESD Design Methods: Method of Substitution; 2.4.1 Method of Substitution of Passive Element to ESD Network Element; 2.4.2 Substitution of ESD Network Element to Passive Element; 2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks; 2.5.1 RF ESD Method - Conversion of Matching Networks to ESD Networks; 2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks; 2.5.2.1 Conversion of ESD Networks into L-Match Networks; 2.5.2.2 Conversion of ESD Networks into Pie-Match Networks 2.5.2.3 Conversion of ESD Networks into T-Match Networks2.6 RF ESD Design Methods: Inductive Shunt; 2.7 RF ESD Design Methods: Cancellation Method; 2.7.1 Quality Factors and the Cancellation Method; 2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit; 2.7.3 Cancellation Method and ESD Circuitry; 2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator; 2.9 RF ESD Design Methods: Lumped versus Distributed Loads; 2.9.1 RF ESD Distributed Load with Coplanar Wave Guides; 2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices 2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration |
| Altri titoli varianti | Electrostatic discharge |
| Record Nr. | UNINA-9910877635203321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : circuits and devices / / Steven H. Voldman
| ESD : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| ISBN |
1-280-28748-9
9786610287482 0-470-01350-8 0-470-01290-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; About the Author; Preface; Acknowledgements; 1 Electrostatics and Electrothermal Physics; 1.1 Introduction; 1.2 A Time Constant Approach; 1.2.1 ESD Time Constants; 1.2.2 Time Constant Hierarchy; 1.2.3 Thermal Time Constant; 1.2.4 Thermal Diffusion; 1.2.5 Adiabatic, Thermal Diffusion Time Scale and Steady State; 1.2.6 Electroquasistatics and Magnetoquasistatics; 1.3 Instability; 1.3.1 Electrical Instability; 1.3.2 Electrothermal Instability; 1.3.3 Spatial Instability and Current Constriction; 1.4 Breakdown; 1.4.1 Paschen's Breakdown Theory; 1.4.2 Townsend's Concept
1.4.3 Toepler's Law1.5 Avalanche Breakdown; 1.5.1 Breakdown in Air; 1.5.2 Air Breakdown and Peak Currents; 1.5.3 Air Breakdown and Rise Times; 1.5.4 Mesoplasmas and Microplasmas; 1.5.5 Mesoplasma Phenomena; Problems; References; 2 Electrothermal Methods and ESD Models; 2.1 Electrothermal Methods; 2.1.1 Green's Function and Method of Images; 2.1.2 Integral Transforms of the Heat Conduction Equation; 2.1.3 Flux Potential Transfer Relations Matrix Methodology; 2.1.4 Heat Equation with Variable Conductivity; 2.1.5 Duhamel Formulation; 2.2 Electrothermal Models; 2.2.1 Tasca Model 2.2.2 Wunsch-Bell Model2.2.3 Smith-Littau Model; 2.2.4 Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model; 2.2.5 Vlasov-Sinkevitch Model; 2.2.6 Dwyer-Franklin-Campbell Model; 2.2.7 Greve Model; 2.2.8 Negative Differential Resistance Model; 2.2.9 Ash Model; 2.2.10 Statistical Models; Problems; References; 3 Semiconductor Devices and ESD; 3.1 Device Physics; 3.1.1 Nonisothermal Simulation; 3.2 Diodes; 3.2.1 Diode Equation; 3.2.2 Recombination and Generation Mechanisms; 3.3 Bipolar High-current Device Physics; 3.3.1 Bipolar Transistor Equation; 3.3.2 Kirk Effect; 3.3.3 Johnson Limit 3.4 Silicon-Controlled Rectifiers3.4.1 Regenerative Feedback; 3.5 Resistors; 3.6 MOSFET High-current Device Physics; 3.6.1 Parasitic Bipolar Transistor Equation; 3.6.2 Avalanche Breakdown and Snapback; 3.6.3 Instability and Current Constriction Model; 3.6.4 Dielectric Breakdown; 3.6.5 Gate Induced Drain Leakage (GIDL); Problems; References; 4 Substrates and ESD; 4.1 Methods of Substrate Analysis; 4.2 Substrate as a Semi-infinite Domain; 4.3 Substrate as a Stratified Medium Using the Transfer Matrix Approach; 4.4 Substrate Transmission Line Model; 4.5 Substrate Lossy Transmission Line Models 4.6 Substrate Absorption, Reflection and Transmission4.7 Substrate Electrical and Thermal Discretization; 4.8 Substrate Effects: Electrical Transfer Resistance; 4.9 Substrate Effects: Thermal Transfer Resistance; 4.10 Substrate Thermal Resistance Models; 4.10.1 Variable Cross-section Model; 4.10.2 Variable Elliptical Cross-section Model; 4.10.3 Back-surface Substrate Lumped Analytical Model; 4.11 Heavily Doped Substrates; 4.12 Low-doped Substrates; Problems; References; 5 Wells, Sub-collectors and ESD; 5.1 Diffused Wells; 5.2 Retrograde and Vertically Modulated Wells; 5.2.1 Retrograde Wells 5.2.2 Retrograde Well Substrate Modulation |
| Altri titoli varianti | Circuits and devices |
| Record Nr. | UNINA-9910876513903321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD basics [[electronic resource] ] : from semiconductor manufacturing to use / / Steven H. Voldman
| ESD basics [[electronic resource] ] : from semiconductor manufacturing to use / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, : Wiley, 2012 |
| Descrizione fisica | 1 online resource (xviii, 208 p. ) : ill |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Electronic apparatus and appliances - Design and construction
Electric discharges Electronic apparatus and appliances - Protection Microelectronics Static eliminators Electrostatics |
| ISBN |
1-118-55907-X
1-118-44332-2 1-118-44326-8 1-118-44327-6 1-283-59903-1 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910132519303321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, : Wiley, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD basics : from semiconductor manufacturing to use / / Steven H. Voldman
| ESD basics : from semiconductor manufacturing to use / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Chichester, West Sussex, : Wiley, 2012 |
| Descrizione fisica | 1 online resource (xviii, 208 p. ) : ill |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Electronic apparatus and appliances - Design and construction
Electric discharges Electronic apparatus and appliances - Protection Microelectronics Static eliminators Electrostatics |
| ISBN |
1-118-55907-X
1-118-44332-2 1-118-44326-8 1-118-44327-6 1-283-59903-1 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD BASICS: From Semiconductor Manufacturing to Product Use -- Contents -- About the Author -- Preface -- Acknowledgments -- 1 Fundamentals of Electrostatics -- 1.1 Introduction -- 1.2 Electrostatics -- 1.2.1 Thales of Miletus and Electrostatic Attraction -- 1.2.2 Electrostatics and the Triboelectric Series -- 1.2.3 Triboelectric Series and Gilbert -- 1.2.4 Triboelectric Series and Gray -- 1.2.5 Triboelectric Series and Dufay -- 1.2.6 Triboelectric Series and Franklin -- 1.2.7 Electrostatics - Symmer and the Human Body Model -- 1.2.8 Electrostatics - Coulomb and Cavendish -- 1.2.9 Electrostatics - Faraday and the Ice Pail Experiment -- 1.2.10 Electrostatics - Faraday and Maxwell -- 1.2.11 Electrostatics - Paschen -- 1.2.12 Electrostatics - Stoney and the "Electron" -- 1.3 Triboelectric Charging - How does it Happen? -- 1.4 Conductors, Semiconductors, and Insulators -- 1.5 Static Dissipative Materials -- 1.6 ESD and Materials -- 1.7 Electrification and Coulomb's Law -- 1.7.1 Electrification by Friction -- 1.7.2 Electrification by Induction -- 1.7.3 Electrification by Conduction -- 1.8 Electromagnetism and Electrodynamics -- 1.9 Electrical Breakdown -- 1.9.1 Electrostatic Discharge and Breakdown -- 1.9.2 Breakdown and Paschen's Law -- 1.9.3 Breakdown and Townsend -- 1.9.4 Breakdown and Toepler's Law -- 1.9.5 Avalanche Breakdown -- 1.10 Electroquasistatics and Magnetoquasistatics -- 1.11 Electrodynamics and Maxwell's Equations -- 1.12 Electrostatic Discharge (ESD) -- 1.13 Electromagnetic Compatibility (EMC) -- 1.14 Electromagnetic Interference (EMI) -- 1.15 Summary and Closing Comments -- References -- 2 Fundamentals of Manufacturing and Electrostatics -- 2.1 Materials, Tooling, Human Factors, and Electrostatic Discharge -- 2.1.1 Materials and Human Induced Electric Fields -- 2.2 Manufacturing Environment and Tooling.
2.3 Manufacturing Equipment and ESD Manufacturing Problems -- 2.4 Manufacturing Materials -- 2.5 Measurement and Test Equipment -- 2.5.1 Manufacturing Testing for Compliance -- 2.6 Grounding and Bonding Systems -- 2.7 Worksurfaces -- 2.8 Wrist Straps -- 2.9 Constant Monitors -- 2.10 Footwear -- 2.11 Floors -- 2.12 Personnel Grounding with Garments -- 2.12.1 Garments -- 2.13 Air Ionization -- 2.14 Seating -- 2.15 Carts -- 2.16 Packaging and Shipping -- 2.16.1 Shipping Tubes -- 2.16.2 Trays -- 2.17 ESD Identification -- 2.18 ESD Program Management - Twelve Steps to Building an ESD Strategy -- 2.19 ESD Program Auditing -- 2.20 ESD On-Chip Protection -- 2.21 Summary and Closing Comments -- References -- 3 ESD, EOS, EMI, EMC and Latchup -- 3.1 ESD, EOS, EMI, EMC and Latchup -- 3.1.1 ESD -- 3.1.2 EOS -- 3.1.3 EMI -- 3.1.4 EMC -- 3.1.5 Latchup -- 3.2 ESD Models -- 3.2.1 Human Body Model (HBM) -- 3.2.2 Machine Model (MM) -- 3.2.3 Cassette Model -- 3.2.4 Charged Device Model (CDM) -- 3.2.5 Transmission Line Pulse (TLP) -- 3.2.6 Very Fast Transmission Line Pulse (VF-TLP) -- 3.3 Electrical Overstress (EOS) -- 3.3.1 EOS Sources - Lightning -- 3.3.2 EOS Sources - Electromagnetic Pulse (EMP) -- 3.3.3 EOS Sources - Machinery -- 3.3.4 EOS Sources - Power Distribution -- 3.3.5 EOS Sources - Switches, Relays and Coils -- 3.3.6 EOS Design Flow and Product Definition -- 3.3.7 EOS Sources - Design Issues -- 3.3.8 EOS Failure Mechanisms -- 3.4 EMI -- 3.5 EMC -- 3.6 Latchup -- 3.7 Summary and Closing Comments -- References -- 4 System Level ESD -- 4.1 System Level Testing -- 4.1.1 System Level Testing Objectives -- 4.1.2 Distinction of System and Component Level Testing Failure Criteria -- 4.2 When Systems and Chips Interact -- 4.3 ESD and System Level Failures -- 4.3.1 ESD Current and System Level Failures -- 4.3.2 ESD Induced E- and H-Fields and System Level Failures. 4.4 Electronic Systems -- 4.4.1 Cards and Boards -- 4.4.2 System Chassis and Shielding -- 4.5 System Level Problems Today -- 4.5.1 Hand Held Systems -- 4.5.2 Cell Phones -- 4.5.3 Servers and Cables -- 4.5.4 Laptops and Cables -- 4.5.5 Disk Drives -- 4.5.6 Digital Cameras -- 4.6 Automobiles, ESD, EOS, and EMI -- 4.6.1 Automobiles and ESD - Ignition Systems -- 4.6.2 Automobiles and EMI - Electronic Pedal Assemblies -- 4.6.3 Automobiles and Gas Tank Fires -- 4.6.4 Hybrids and Electric Cars -- 4.6.5 Automobiles in the Future -- 4.7 Aerospace Applications -- 4.7.1 Airplanes, Partial Discharge, and Lightning -- 4.7.2 Satellites, Spacecraft Charging, and Single Event Upset (SEU) -- 4.7.3 Space Landing Missions -- 4.8 ESD and System Level Test Models -- 4.9 IEC 61000-4-2 -- 4.10 Human Metal Model (HMM) -- 4.11 Charged Board Model (CBM) -- 4.12 Cable Discharge Event (CDE) -- 4.12.1 Cable Discharge Event (CDE) and Scaling -- 4.12.2 Cable Discharge Event (CDE) - Cable Measurement Equipment -- 4.12.3 Cable Configuration - Test Configuration -- 4.12.4 Cable Configuration - Floating Cable -- 4.12.5 Cable Configuration - Held Cable -- 4.12.6 Cable Discharge Event (CDE) - Peak Current vs. Charged Voltage -- 4.12.7 Cable Discharge Event (CDE) - Plateau Current vs Charged Voltage -- 4.13 Summary and Closing Comments -- References -- 5 Component Level Issues - Problems and Solutions -- 5.1 ESD Chip Protection - The Problem and the Cure -- 5.2 ESD Chip Level Design Solutions - Basics of Design Synthesis -- 5.2.1 ESD Circuits -- 5.2.2 ESD Signal Pin Protection Networks -- 5.2.3 ESD Power Clamp Protection Networks -- 5.2.4 ESD Power Domain-to-Domain Circuitry -- 5.2.5 ESD Internal Signal Line Domain-to-Domain Protection Circuitry -- 5.3 ESD Chip Floor Planning - Basics of Design Layout and Synthesis -- 5.3.1 Placement of ESD Signal Pin HBM Circuitry. 5.3.2 Placement of ESD Signal Pin CDM Circuitry -- 5.3.3 Placement of ESD Power Clamp Circuitry -- 5.3.4 Placement of ESD VSS-to-VSS Circuitry -- 5.4 ESD Analog Circuit Design -- 5.4.1 Symmetry and Common Centroid Design for ESD Analog Circuits -- 5.4.2 Analog Signal Pin to Power Rail ESD Network -- 5.4.3 Common Centroid Analog Signal Pin to Power Rail ESD Network -- 5.4.4 Co-synthesis of Common Centroid Analog Circuit and ESD Networks -- 5.4.5 Signal Pin-to-Signal Pin Differential Pair ESD Network -- 5.4.6 Common Centroid Signal Pin Differential Pair ESD Protection -- 5.5 ESD Radio Frequency (RF) Design -- 5.5.1 ESD Radio Frequency (RF) Design Practices -- 5.5.2 ESD RF Circuits - Signal Pin ESD Networks -- 5.5.3 ESD RF Circuits - ESD Power Clamps -- 5.5.4 ESD RF Circuits - ESD RF VSS-to-VSS Networks -- 5.6 Summary and Closing Comments -- References -- 6 ESD in Systems - Problems and Solutions -- 6.1 ESD System Solutions from Largest to Smallest -- 6.2 Aerospace Solutions -- 6.3 Oil Tanker Solutions -- 6.4 Automobile Solutions -- 6.5 Computers - Servers -- 6.5.1 Servers - Touch Pads and Handling Procedures -- 6.6 Mother Boards and Cards -- 6.6.1 System Card Insertion Contacts -- 6.6.2 System Level Board Design - Ground Design -- 6.7 System Level "On Board" ESD Protection -- 6.7.1 Spark Gaps -- 6.7.2 Field Emission Devices (FED) -- 6.8 System Level Transient Solutions -- 6.8.1 Transient Voltage Suppression (TVS) Devices -- 6.8.2 Polymer Voltage Suppression (PVS) Devices -- 6.9 Package-Level Mechanical ESD Solutions - Mechanical "Crowbars" -- 6.10 Disk Drive ESD Solutions -- 6.10.1 In Line "ESD Shunt" -- 6.10.2 Armature - Mechanical "Shunt" - A Built-In Electrical "Crowbar" -- 6.11 Semiconductor Chip Level Solutions - Floor Planning, Layout, and Architecture -- 6.11.1 Mixed Signal Analog and Digital Floor Planning. 6.11.2 Bipolar-CMOS-DMOS (BCD) Floor Planning -- 6.11.3 System-on Chip Design Floor Planning -- 6.12 Semiconductor Chip Solutions - Electrical Power Grid Design -- 6.12.1 HMM and IEC Specification Power Grid and Interconnect Design Considerations -- 6.12.2 ESD Power Clamp Design Synthesis - IEC 61000-4-2 Responsive ESD Power Clamps -- 6.13 ESD and EMC - When Chips Bring Down Systems -- 6.14 System Level and Component Level ESD Testing and System Level Response -- 6.14.1 Time Domain Reflection (TDR) and Impedance Methodology for ESD Testing -- 6.14.2 Time Domain Reflectometry (TDR) ESD Test System Evaluation -- 6.14.3 ESD Degradation System Level Method - Eye Tests -- 6.15 EMC and ESD Scanning -- 6.16 Summary and Closing Comments -- References -- 7 Electrostatic Discharge (ESD) in the Future -- 7.1 What is in the Future for ESD? -- 7.2 Factories and Manufacturing -- 7.3 Photo-Masks and Reticles -- 7.3.1 ESD Concerns in Photo-Masks -- 7.3.2 Avalanche Breakdown in Photo-Masks -- 7.3.3 Electrical Model in Photo-Masks -- 7.3.4 Failure Defects in Photo-Masks -- 7.4 Magnetic Recording Technology -- 7.5 Micro-Electromechanical (MEM) Devices -- 7.5.1 ESD Concerns in Micro-Electromechanical (MEM) Devices -- 7.6 Micro-Motors -- 7.6.1 ESD Concerns in Micro-Motors -- 7.7 Micro-Electromechanical (MEM) RF Switches -- 7.7.1 ESD Concerns in Micro-Electromechanical (MEM) RF Switches -- 7.8 Micro-Electromechanical (MEM) Mirrors -- 7.8.1 ESD Concerns in Micro-Electromechanical (MEM) Mirrors -- 7.9 Transistors -- 7.9.1 Transistors - Bulk vs. SOI Technology -- 7.9.2 Transistors and FinFETs -- 7.9.3 ESD in FinFETs -- 7.10 Silicon Nanowires -- 7.11 Carbon Nanotubes -- 7.12 Future Systems and System Designs -- 7.13 Summary and Closing Comments -- References -- Glossary -- ESD Standards -- Index. |
| Record Nr. | UNINA-9910814947703321 |
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Voldman Steven H
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| Chichester, West Sussex, : Wiley, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ESD in silicon integrated circuits
| ESD in silicon integrated circuits |
| Autore | Amerasekera E. A |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | [Place of publication not identified], : J Wiley, 2002 |
| Descrizione fisica | 1 online resource (421 pages) |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Static eliminators Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-280-55472-X
9786610554720 0-470-85212-7 0-470-84605-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146249503321 |
|
Amerasekera E. A
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| [Place of publication not identified], : J Wiley, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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