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Algebraic structure theory of sequential machines / J. Hartmanis, R.E. Stearns
| Algebraic structure theory of sequential machines / J. Hartmanis, R.E. Stearns |
| Autore | Hartmanis, J. |
| Pubbl/distr/stampa | Englewood Cliffs, N.J. : Prentice-Hall, 1966 |
| Descrizione fisica | viii, 211 p. : ill. ; 24 cm. |
| Altri autori (Persone) | Stearns, R. E. |
| Collana | Prentice-Hall series in automatic computation |
| Soggetto topico | Sequential machine theory |
| Classificazione |
510.78
621.3.9.1 QA267.5.S4H3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991000804729707536 |
Hartmanis, J.
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| Englewood Cliffs, N.J. : Prentice-Hall, 1966 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Automata, languages and programming : 2nd Colloquium, University of Saarbrücken, July 29 - August 2, 1974 / / edited by J. Loeckx
| Automata, languages and programming : 2nd Colloquium, University of Saarbrücken, July 29 - August 2, 1974 / / edited by J. Loeckx |
| Edizione | [1st ed. 1974.] |
| Pubbl/distr/stampa | Berlin ; ; Heidelberg ; ; New York : , : Springer-Verlag Berlin Heidelberg GmbH, , [1974] |
| Descrizione fisica | 1 online resource (619 p.) |
| Disciplina | 511.3 |
| Collana | Lecture notes in computer science |
| Soggetto topico | Sequential machine theory |
| ISBN |
3-540-37778-6
3-662-21545-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | The generative power of two-level grammars -- A generalisation of Parikh's theorem in formal language theory -- Checking stacks and context-free programmed grammars accept p-complete languages -- Recursion and parameter mechanisms: An axiomatic approach -- Dynamic programming schemata -- Semantic characterization of flow diagrams and their decomposability -- On the most recent property of ALGOL-like programs -- Langages sans etiquettes et transformations de programmes -- Relations between semantics and complexity of recursive programs- -- On the relation between direct and continuation semantics -- Graph representation and computation rules for typeless recursive languages -- Application of Church-Rosser properties to increase the parallelism and efficiency of algorithms -- Combinatorial problems, combinator equations and normal forms -- Algorithmes d'Equivalence et de reduction a des expressions minimales dans une classe d'equations recursives simples -- Automatic generation of multiple exit parsing subroutines -- Production prefix parsing -- On eliminating unit productions from LR(k) parsers -- Deterministic techniques for efficient non-deterministic parsers -- File organization, an application of graph theory -- Characterizations of time-bounded computations by limited primitive recursion -- On maximal merging of information in Boolean computations -- On simple Goedel numberings and translations -- The ‘almost all’ theory of subrecursive degrees is decidable -- The computational complexity of program schemata -- Un resultat en theorie des groupes de permutations et son application au calcul effectif du groupe d'automorphismes d'un automate fini -- Sur l'Application du theoreme de suschkewitsch a l'etude des codes rationnels complets -- Composition of automata -- Context-free grammar forms -- Une suite decroissante de cônes rationnels -- Komplexitätsmaße for Ausdrocke -- Efficient procedures for using matrix algorithms -- Further schemes for combining matrix algorithms -- On the structure of complexity classes -- On sets having only hard subsets -- Turing machines with associative memory access -- Trade-off between the use of nonterminals, codings and homomorphisms in defining languages for some classes of rewriting systems -- Operators reducing generalized OL-systems -- Parallel rewriting systems on terms -- Transductions of context-free languages into sets of sentential forms -- Parallelism in rewriting systems -- Mehrdeutigkeiten kontextfreier Grammatiken -- Monadic program schemes under restricted classes of free interpretations -- Generalized program schemas -- A decidability result for sequential grammars -- Effectivity problems of algorithmic logic -- Simple and structural redundancy in non-deterministic computation -- Sur une propriete syntactique des relations rationnelles. |
| Record Nr. | UNISA-996465409103316 |
| Berlin ; ; Heidelberg ; ; New York : , : Springer-Verlag Berlin Heidelberg GmbH, , [1974] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Automata, languages, and machines / Samuel Eilenberg
| Automata, languages, and machines / Samuel Eilenberg |
| Autore | Eilenberg, Samuel |
| Pubbl/distr/stampa | New York : Academic Press, 1974-76 |
| Descrizione fisica | 2 v. ; 24 cm. |
| Disciplina | 005.131 |
| Collana |
Pure and applied mathematics. A series of monographs & textbooks [Academic Press], 0079-8169 ; 59-A
Pure and applied mathematics. A series of monographs & textbooks [Academic Press], 0079-8169 ; 59-B |
| Soggetto topico |
Automata theory
Formal languages Sequential machine theory |
| ISBN |
0122340019 (v. A)
0122340027 (v. B) |
| Classificazione | AMS 68Q68 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991000708099707536 |
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Eilenberg, Samuel
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| New York : Academic Press, 1974-76 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Buchi's monadic second order successor arithmetic / Dirk Siefkes
| Buchi's monadic second order successor arithmetic / Dirk Siefkes |
| Autore | Siefkes, Dirk |
| Pubbl/distr/stampa | Berlin ; New York : Springer-Verlag, 1970 |
| Descrizione fisica | xii, 130 p. ; 26 cm |
| Disciplina | 511.65 |
| Collana |
Decidable theories ; 1
Lecture notes in mathematics, 0075-8434 ; 120 |
| Soggetto topico |
Decidability
Predicate calculus Sequential machine theory |
| Classificazione |
AMS 11U05
QA3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991000724409707536 |
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Siefkes, Dirk
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| Berlin ; New York : Springer-Verlag, 1970 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Computability and decidability : an introduction for students of computer science / J. Loeckx
| Computability and decidability : an introduction for students of computer science / J. Loeckx |
| Autore | Loeckx, Jacques J. C. |
| Pubbl/distr/stampa | Berlin : Springer-Verlag, 1972 |
| Descrizione fisica | vi, 76 p. : ill. ; 26 cm. |
| Disciplina | 001.535 |
| Collana | Lecture notes in economics and mathematical systems, 0075-8442 ; 68 |
| Soggetto topico |
Automata theory
Programming Sequential machine theory Turing machines |
| ISBN | 3540058699 |
| Classificazione |
AMS 68N05
AMS 68Q68 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991000772929707536 |
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Loeckx, Jacques J. C.
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| Berlin : Springer-Verlag, 1972 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Digital electronics . 3 Finite-state machines / / Tertulien Ndjountche
| Digital electronics . 3 Finite-state machines / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : iSTE : , : Wiley, , 2016 |
| Descrizione fisica | 1 online resource (335 pages) : illustrations |
| Disciplina | 621.381 |
| Collana | Electronics Engineering Series |
| Soggetto topico |
Digital electronics
Sequential machine theory |
| ISBN |
1-119-37108-2
1-119-37111-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910148573703321 |
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Ndjountche Tertulien
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| London, England ; ; Hoboken, New Jersey : , : iSTE : , : Wiley, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital electronics . 3 Finite-state machines / / Tertulien Ndjountche
| Digital electronics . 3 Finite-state machines / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : iSTE : , : Wiley, , 2016 |
| Descrizione fisica | 1 online resource (335 pages) : illustrations |
| Disciplina | 621.381 |
| Collana | Electronics Engineering Series |
| Soggetto topico |
Digital electronics
Sequential machine theory |
| ISBN |
1-119-37108-2
1-119-37111-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910824534703321 |
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Ndjountche Tertulien
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| London, England ; ; Hoboken, New Jersey : , : iSTE : , : Wiley, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital system design using FSMs : a practical learning approach / / Peter D. Minns
| Digital system design using FSMs : a practical learning approach / / Peter D. Minns |
| Autore | Minns Peter D. |
| Pubbl/distr/stampa | Hoboken, NJ : , : John Wiley & Sons, Inc., , 2021 |
| Descrizione fisica | 1 online resource (340 pages) |
| Disciplina | 621.381 |
| Soggetto topico |
Digital electronics
Sequential machine theory |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-119-78272-4
1-119-78271-6 1-119-78273-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Acknowledgements -- About the Companion Website -- Guide to Supplementary Resources -- Chapter 1 Introduction to Finite State Machines -- 1.1 Some Notes on Style -- Chapter 2 Using FSMs to Control External Devices -- 2.1 Introduction -- Chapter 3 Introduction to FSM Synthesis -- 3.1 Introduction -- 3.2 Tutorials Covering Chapters 1, 2, and 3 -- 3.2.1 Binary data serial transmitter FSM -- 3.2.2 The high low FSM system -- 3.2.3 The clocked watchdog timer FSM -- 3.2.4 The asynchronous receiver system clocked FSM -- Chapter 4 Asynchronous FSM Methods -- 4.1 Introduction to Asynchronous FSM -- 4.2 Summary -- 4.3 Tutorials -- 4.3.1 FSM motor with fault detection -- 4.3.2 The mower in four and two states -- Chapter 5 Clocked One Hot Method of FSM Design -- 5.1 Introduction -- 5.2 Tutorials on the Clocked one Hot FSM Method -- 5.2.1 Seven-state system clocked one hot method -- 5.2.2 Memory tester FSM -- 5.2.3 Eight-bit sequence detector FSM -- Chapter 6 Further Event-Driven FSM Design -- 6.1 Introduction -- 6.2 Conclusions -- Chapter 7 Petri Net FSM Design -- 7.1 Introduction -- 7.2 Tutorials Using Petri Net FSM -- 7.2.1 Controlled shared resource Petri nets -- 7.2.2 Serial clock-driven Petri net FSM -- 7.2.3 Using asynchronous (event-driven) design with Petri nets -- 7.3 Conclusions -- Appendix A1: Boolean Algebra -- A1.1 Basic Gate Symbols -- A1.2 The Exclusive OR and Exclusive NOR -- A1.3 Laws of Boolean Algebra -- A1.3.1 Basic OR rules -- A1.3.2 Basic AND rules -- A1.3.3 Associative and commutative laws -- A1.3.4 Distributive laws -- A1.3.5 Auxiliary rule for static 1 hazard removal -- A1.3.6 Consensus theorem -- A1.3.7 The effect of signal delay in logic gates -- A1.3.8 De-Morgan's theorem -- A1.4 Examples of Applying the Laws of Boolean Algebra -- A1.4.1 Converting AND-OR to NAND.
A1.4.2 Converting AND-OR to NOR -- A1.4.3 Logical adjacency rule -- A1.5 Summary -- Appendix A2: Use of Verilog HDL and Logisim to FSM -- A2.1 The Single-Pulse Generator with Memory Clock-Driven FSM -- A2.2 Test Bench Module and its Purpose -- A2.3 Using Synapticad Software -- A2.4 More Direct Method -- A2.5 A Very Simple Guide to Using the Logisim Simulator -- A2.5.1 The Logisim top level menu items -- A2.6 Using Flip-Flops in a Circuit -- A2.7 Example Single-Pulse FSM -- A2.8 How to Use the Simulator to Simulate the Single-Pulse FSM -- A2.8.1 Using Logisim with the truth table approach -- A2.9 Using Logisim with the Truth Table Approach -- A2.9.1 Useful note -- A2.10 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A3.1 Basic Down Synchronous Binary Counter Development -- A3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops -- A3.3 Parallel Loading Counters - Using T Flip-Flops -- A3.4 Using D Flip-Flops To Build Parallel Loading Counters -- A3.5 Simple Binary Up Counter with Parallel Inputs -- A3.6 Clock Circuit to Drive the Counter (and FSM) -- A3.7 Counter Design Using Don't Care States -- A3.8 Shift Registers -- A3.9 Dealing with Input and Output Signals Using FSM -- A3.10 Using Logisim to Work with Larger FSM Systems -- A3.10.1 The equations -- A3.11 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A4.1 Introduction -- A4.2 The Single-Pulse/Multiple-Pulse Generator with Memory FSM -- A4.3 The Memory Tester FSM Revisited -- A4.4 Summary -- Appendix A5: Programming a Finite State Machine -- A5.1 Introduction -- A5.2 The Parallel Loading Counter -- A5.3 The Multiplexer -- A5.4 The Micro Instruction -- A5.5 The Memory -- A5.6 The Instruction Set -- A5.7 Simple Example: Single-Pulse FSM -- A5.8 The Final Example. A5.9 The Program Code -- A5.10 Returning Unused States Via Other Transition Paths -- A5.11 Summary -- Appendix A6: The Rotational Detector Using Logisim Simulator with Sub-Circuits -- A6.1 Using the Two-State Diagram Arrangement -- Bibliography -- Index -- EULA. |
| Record Nr. | UNINA-9910555070703321 |
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Minns Peter D.
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| Hoboken, NJ : , : John Wiley & Sons, Inc., , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital system design using FSMs : a practical learning approach / / Peter D. Minns
| Digital system design using FSMs : a practical learning approach / / Peter D. Minns |
| Autore | Minns Peter D. |
| Pubbl/distr/stampa | Hoboken, NJ : , : John Wiley & Sons, Inc., , 2021 |
| Descrizione fisica | 1 online resource (340 pages) |
| Disciplina | 621.381 |
| Soggetto topico |
Digital electronics
Sequential machine theory |
| ISBN |
1-119-78272-4
1-119-78271-6 1-119-78273-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Acknowledgements -- About the Companion Website -- Guide to Supplementary Resources -- Chapter 1 Introduction to Finite State Machines -- 1.1 Some Notes on Style -- Chapter 2 Using FSMs to Control External Devices -- 2.1 Introduction -- Chapter 3 Introduction to FSM Synthesis -- 3.1 Introduction -- 3.2 Tutorials Covering Chapters 1, 2, and 3 -- 3.2.1 Binary data serial transmitter FSM -- 3.2.2 The high low FSM system -- 3.2.3 The clocked watchdog timer FSM -- 3.2.4 The asynchronous receiver system clocked FSM -- Chapter 4 Asynchronous FSM Methods -- 4.1 Introduction to Asynchronous FSM -- 4.2 Summary -- 4.3 Tutorials -- 4.3.1 FSM motor with fault detection -- 4.3.2 The mower in four and two states -- Chapter 5 Clocked One Hot Method of FSM Design -- 5.1 Introduction -- 5.2 Tutorials on the Clocked one Hot FSM Method -- 5.2.1 Seven-state system clocked one hot method -- 5.2.2 Memory tester FSM -- 5.2.3 Eight-bit sequence detector FSM -- Chapter 6 Further Event-Driven FSM Design -- 6.1 Introduction -- 6.2 Conclusions -- Chapter 7 Petri Net FSM Design -- 7.1 Introduction -- 7.2 Tutorials Using Petri Net FSM -- 7.2.1 Controlled shared resource Petri nets -- 7.2.2 Serial clock-driven Petri net FSM -- 7.2.3 Using asynchronous (event-driven) design with Petri nets -- 7.3 Conclusions -- Appendix A1: Boolean Algebra -- A1.1 Basic Gate Symbols -- A1.2 The Exclusive OR and Exclusive NOR -- A1.3 Laws of Boolean Algebra -- A1.3.1 Basic OR rules -- A1.3.2 Basic AND rules -- A1.3.3 Associative and commutative laws -- A1.3.4 Distributive laws -- A1.3.5 Auxiliary rule for static 1 hazard removal -- A1.3.6 Consensus theorem -- A1.3.7 The effect of signal delay in logic gates -- A1.3.8 De-Morgan's theorem -- A1.4 Examples of Applying the Laws of Boolean Algebra -- A1.4.1 Converting AND-OR to NAND.
A1.4.2 Converting AND-OR to NOR -- A1.4.3 Logical adjacency rule -- A1.5 Summary -- Appendix A2: Use of Verilog HDL and Logisim to FSM -- A2.1 The Single-Pulse Generator with Memory Clock-Driven FSM -- A2.2 Test Bench Module and its Purpose -- A2.3 Using Synapticad Software -- A2.4 More Direct Method -- A2.5 A Very Simple Guide to Using the Logisim Simulator -- A2.5.1 The Logisim top level menu items -- A2.6 Using Flip-Flops in a Circuit -- A2.7 Example Single-Pulse FSM -- A2.8 How to Use the Simulator to Simulate the Single-Pulse FSM -- A2.8.1 Using Logisim with the truth table approach -- A2.9 Using Logisim with the Truth Table Approach -- A2.9.1 Useful note -- A2.10 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A3.1 Basic Down Synchronous Binary Counter Development -- A3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops -- A3.3 Parallel Loading Counters - Using T Flip-Flops -- A3.4 Using D Flip-Flops To Build Parallel Loading Counters -- A3.5 Simple Binary Up Counter with Parallel Inputs -- A3.6 Clock Circuit to Drive the Counter (and FSM) -- A3.7 Counter Design Using Don't Care States -- A3.8 Shift Registers -- A3.9 Dealing with Input and Output Signals Using FSM -- A3.10 Using Logisim to Work with Larger FSM Systems -- A3.10.1 The equations -- A3.11 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A4.1 Introduction -- A4.2 The Single-Pulse/Multiple-Pulse Generator with Memory FSM -- A4.3 The Memory Tester FSM Revisited -- A4.4 Summary -- Appendix A5: Programming a Finite State Machine -- A5.1 Introduction -- A5.2 The Parallel Loading Counter -- A5.3 The Multiplexer -- A5.4 The Micro Instruction -- A5.5 The Memory -- A5.6 The Instruction Set -- A5.7 Simple Example: Single-Pulse FSM -- A5.8 The Final Example. A5.9 The Program Code -- A5.10 Returning Unused States Via Other Transition Paths -- A5.11 Summary -- Appendix A6: The Rotational Detector Using Logisim Simulator with Sub-Circuits -- A6.1 Using the Two-State Diagram Arrangement -- Bibliography -- Index -- EULA. |
| Record Nr. | UNINA-9910830781803321 |
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Minns Peter D.
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| Hoboken, NJ : , : John Wiley & Sons, Inc., , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Finite state machine logic synthesis for complex programmable logic devices / / Robert Czerwinski and Dariusz Kania
| Finite state machine logic synthesis for complex programmable logic devices / / Robert Czerwinski and Dariusz Kania |
| Autore | Czerwinski Robert |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Heidelberg [Germany] : , : Springer, , 2013 |
| Descrizione fisica | 1 online resource (xiv, 172 pages) : illustrations |
| Disciplina |
621.39/5
621.395 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Programmable logic devices
Sequential machine theory |
| ISBN | 3-642-36166-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Theoretical Background of Technology-Dependent Optimization -- The Algorithm of Area Optimization Based on Graphs of Outputs -- Conclusions -- Output File Format -- Conclusion. |
| Record Nr. | UNINA-9910437913103321 |
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Czerwinski Robert
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| Heidelberg [Germany] : , : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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