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2000 IEEE International Conference on Semiconductor Electronics Proceedings
| 2000 IEEE International Conference on Semiconductor Electronics Proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2000 |
| Altri autori (Persone) |
ShaariSahbudin
MajlisBurhanuddin Yeop |
| Soggetto topico |
Semiconductors
Semiconductors - Failures Microelectronic packaging |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996199308603316 |
| [Place of publication not identified], : I E E E, 2000 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits : 16-19 July 2018, Singapore / / Institute of Electrical and Electronics Engineers
| 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits : 16-19 July 2018, Singapore / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (146 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Reliability
Integrated circuits - Testing Semiconductors - Failures |
| ISBN | 1-5386-4929-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996279928603316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits : 16-19 July 2018, Singapore / / Institute of Electrical and Electronics Engineers
| 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits : 16-19 July 2018, Singapore / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (146 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Reliability
Integrated circuits - Testing Semiconductors - Failures |
| ISBN | 1-5386-4929-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910284450903321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910139024303321 |
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910810547003321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman
| ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Record Nr. | UNINA-9910139802703321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman
| ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Record Nr. | UNINA-9910817124503321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ICSE '98 : 1998 IEEE International Conference on Semiconductor Electronics : proceedings : November 24-26, 1998, Equatorial Hotel, Bangi, Malaysia / / edited by Sahbudin Shaari ; technically co-sponsored by IEEE Electron Devices Society
| ICSE '98 : 1998 IEEE International Conference on Semiconductor Electronics : proceedings : November 24-26, 1998, Equatorial Hotel, Bangi, Malaysia / / edited by Sahbudin Shaari ; technically co-sponsored by IEEE Electron Devices Society |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1998 |
| Descrizione fisica | 1 online resource (vii, 259 pages) |
| Disciplina | 621.381046 |
| Soggetto topico |
Microelectronic packaging
Semiconductors - Failures |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996199447703316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IPFA : proceedings of the 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits : June 30, 2014-July 4, 2014, Marina Bay Sands, Singapore / / organised by IEEE, IEEE Singapore Reliability/CPMT/ED Chapter ; technically co-sponsored by IEEE Electron Devices Society, Reliability Society
| IPFA : proceedings of the 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits : June 30, 2014-July 4, 2014, Marina Bay Sands, Singapore / / organised by IEEE, IEEE Singapore Reliability/CPMT/ED Chapter ; technically co-sponsored by IEEE Electron Devices Society, Reliability Society |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 |
| Descrizione fisica | 1 online resource (291 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Reliability
Integrated circuits - Testing Semiconductors - Failures Integrated circuits - Defects |
| ISBN | 1-4799-3929-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910141899703321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IPFA : proceedings of the 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits : June 30, 2014-July 4, 2014, Marina Bay Sands, Singapore / / organised by IEEE, IEEE Singapore Reliability/CPMT/ED Chapter ; technically co-sponsored by IEEE Electron Devices Society, Reliability Society
| IPFA : proceedings of the 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits : June 30, 2014-July 4, 2014, Marina Bay Sands, Singapore / / organised by IEEE, IEEE Singapore Reliability/CPMT/ED Chapter ; technically co-sponsored by IEEE Electron Devices Society, Reliability Society |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 |
| Descrizione fisica | 1 online resource (291 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Reliability
Integrated circuits - Testing Semiconductors - Failures Integrated circuits - Defects |
| ISBN | 1-4799-3929-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996281136103316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
