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1996 1st International Symposium on Plasma Process-Induced Damage : 13-14 May 1996, Santa Clara, California, USA
| 1996 1st International Symposium on Plasma Process-Induced Damage : 13-14 May 1996, Santa Clara, California, USA |
| Pubbl/distr/stampa | [Place of publication not identified], : Northern California Chapter of the American Vacuum Society, 1996 |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Semiconductor wafers
Semiconductors - Effect of radiation on Plasma radiation - Congresses Electrical & Computer Engineering Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872918203321 |
| [Place of publication not identified], : Northern California Chapter of the American Vacuum Society, 1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910144685303321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910829969203321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
9781283869676
1283869675 9783527623068 352762306X 9783527623051 3527623051 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9911018807403321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of wafer bonding [[electronic resource] /] / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo
| Handbook of wafer bonding [[electronic resource] /] / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo |
| Pubbl/distr/stampa | Weinheim, Germany, : Wiley-VCH, 2012 |
| Descrizione fisica | 1 online resource (430 p.) |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
RammPeter
LuJames Jian-Qiang TakloMaaike M. V |
| Soggetto topico |
Semiconductors - Bonding
Semiconductor wafers Microelectromechanical systems - Design and construction |
| ISBN |
3-527-64423-7
1-280-66282-4 9786613639752 3-527-64422-9 3-527-64424-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. 1. Technologies -- pt. 2. Applications. |
| Record Nr. | UNINA-9910139699603321 |
| Weinheim, Germany, : Wiley-VCH, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of wafer bonding / / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo
| Handbook of wafer bonding / / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Weinheim, Germany, : Wiley-VCH, 2012 |
| Descrizione fisica | 1 online resource (430 p.) |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
RammPeter
LuJames Jian-Qiang TakloMaaike M. V |
| Soggetto topico |
Semiconductors - Bonding
Semiconductor wafers Microelectromechanical systems - Design and construction |
| ISBN |
9786613639752
9783527644230 3527644237 9781280662829 1280662824 9783527644223 3527644229 9783527644247 3527644245 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. 1. Technologies -- pt. 2. Applications. |
| Record Nr. | UNINA-9910815016903321 |
| Weinheim, Germany, : Wiley-VCH, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Interlayer dielectrics for semiconductor technologies [e-book] / edited by S.P. Murarka, M. Eizenberg, A.K. Sinha
| Interlayer dielectrics for semiconductor technologies [e-book] / edited by S.P. Murarka, M. Eizenberg, A.K. Sinha |
| Pubbl/distr/stampa | Amsterdam ; Boston : Elsevier/Academic Press, 2003 |
| Descrizione fisica | xiv, 444 p. : ill. ; 25 cm |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
Murarka, S. P.
Eizenberg, Moshe Sinha, Ashok K. |
| Soggetto topico |
Semiconductor wafers
Dielectrics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
9780125112215
0125112211 |
| Formato | Risorse elettroniche  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Dialectric Properties, Characterization of Low Dielectric Constant Materials, Compatibilities of Dielectric Film, Silicon Based Dielectrics, Low K Polymers, Chemical Vapour Deposition of CF Low K Materials, Nanoporous Dielectric Films: Fundamental Property Relations and Microelectronic Applications, High K Dielectrics Grown by Atomic Layer Disposition, Dielectric Materials in Optical Waveguide Applications, Reliability, Future Trends in Silicon Technologies |
| Record Nr. | UNISALENTO-991003235189707536 |
| Amsterdam ; Boston : Elsevier/Academic Press, 2003 | ||
| Risorse elettroniche | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
Non-destructive damping measurement for wafer-level packaged microelectromechanical system (MEMS) acceleration switches / / Ryan Knight and Evan Cheng
| Non-destructive damping measurement for wafer-level packaged microelectromechanical system (MEMS) acceleration switches / / Ryan Knight and Evan Cheng |
| Autore | Knight Ryan |
| Pubbl/distr/stampa | Adelphi, MD : , : Army Research Laboratory, , September 2014 |
| Descrizione fisica | 1 online resource (v, 29 pages) : color illustrations |
| Collana | ARL-TR |
| Soggetto topico |
Microelectromechanical systems
Microelectronic packaging Semiconductor wafers |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Non-destructive damping measurement for wafer-level packaged microelectromechanical system |
| Record Nr. | UNINA-9910698637303321 |
Knight Ryan
|
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| Adelphi, MD : , : Army Research Laboratory, , September 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Production planning and control for semiconductor wafer fabrication facilities : modeling, analysis, and systems / / Lars Monch, John W. Fowler, Scott J. Mason
| Production planning and control for semiconductor wafer fabrication facilities : modeling, analysis, and systems / / Lars Monch, John W. Fowler, Scott J. Mason |
| Autore | Mönch Lars |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, : Springer, 2013 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
FowlerJohn W
MasonScott J |
| Collana | Operations research/computer science interfaces series |
| Soggetto topico |
Semiconductor wafers
Microelectronics industry - Production control Production planning |
| ISBN |
1-283-62416-8
9786613936615 1-4614-4472-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Semiconductor Manufacturing Process Description -- Modeling and Analysis Tools -- Dispatching Approaches -- Deterministic Scheduling Approaches -- Order Release Approaches -- Production Planning Approaches -- Production Planning and Control Systems. |
| Record Nr. | UNINA-9910438083703321 |
|
Mönch Lars
|
||
| New York, : Springer, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Wafer manufacturing : shaping of single crystal silicon wafers / / Imin Kao, Chunhui Chung
| Wafer manufacturing : shaping of single crystal silicon wafers / / Imin Kao, Chunhui Chung |
| Autore | Kao Imin |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : John Wiley & Sons, Incorporated, , [2021] |
| Descrizione fisica | 1 online resource (307 pages) : illustrations |
| Disciplina | 621.38152 |
| Soggetto topico | Semiconductor wafers |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-118-69625-5
1-118-69623-9 1-118-69622-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910555197003321 |
|
Kao Imin
|
||
| Hoboken, New Jersey : , : John Wiley & Sons, Incorporated, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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