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Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
| Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XVIII, 602 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Arithmetic and logic units, Computer Input-output equipment (Computers) Microprocessors Computer communication systems Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Register-Transfer-Level Implementation Computer Communication Networks Processor Architectures |
| ISBN | 3-540-30102-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Address I -- Some Real Observations on Virtual Machines -- Session 1A: Cache and Memory -- Replica Victim Caching to Improve Reliability of In-Cache Replication -- Efficient Victim Mechanism on Sector Cache Organization -- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy -- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures -- Session 1B: Reconfigurable and Embedded Architectures -- A Configurable System-on-Chip Architecture for Embedded Devices -- An Auto-adaptative Reconfigurable Architecture for the Control -- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory -- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System -- Session 2A: Processor Architecture and Design I -- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP -- TengYue-1: A High Performance Embedded SoC -- A Fault-Tolerant Single-Chip Multiprocessor -- Session 2B: Power and Energy Management -- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy -- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization -- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption -- Session 3A: Processor Architecture and Design II -- Dynamic Reallocation of Functional Units in Superscalar Processors -- Multiple-Dimension Scalable Adaptive Stream Architecture -- Impact of Register-Cache Bandwidth Variation on Processor Performance -- Session 3B: Compiler and Operating System Issues -- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling -- Continuous Adaptive Object-Code Re-optimization Framework -- Initial Evaluation of a User-Level Device Driver Framework -- Keynote Address II -- A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? -- Session 4A: Application-Specific Systems -- A Cost-Effective Supersampling for Full Scene AntiAliasing -- A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) -- Scalable Design Framework for JPEG2000 System Architecture -- Real-Time Three Dimensional Vision -- Session 4B: Interconnection Networks -- A Router Architecture for QoS Capable Clusters -- Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability -- Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube -- A Two-Level On-Chip Bus System Based on Multiplexers -- Keynote Address III -- Make Computers Cheaper and Simpler -- Session 5A: Prediction Techniques -- A Low Power Branch Predictor to Selectively Access the BTB -- Static Techniques to Improve Power Efficiency of Branch Predictors -- Choice Predictor for Free -- Performance Impact of Different Data Value Predictors -- Session 5B: Parallel Architecture and Programming -- Heterogeneous Networks of Workstations -- Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays -- Order Independent Transparency for Image Composition Parallel Rendering Machines -- An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid Environments -- Session 6A: Microarchitecture Design and Evaluations -- Validating Word-Oriented Processors for Bit and Multi-word Operations -- Dynamic Fetch Engine for Simultaneous Multithreaded Processors -- A Novel Rename Register Architecture and Performance Analysis -- Session 6B: Memory and I/O Systems -- A New Hierarchy Cache Scheme Using RAM and Pagefile -- An Object-Oriented Data Storage System on Network-Attached Object Devices -- A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory -- Session 7A: Potpourri -- A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking -- A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel -- Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization. |
| Record Nr. | UNISA-996465379503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Advances in Computer Systems Architecture : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
| Advances in Computer Systems Architecture : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XVIII, 602 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer architecture
Computer arithmetic and logic units Computer input-output equipment Microprocessors Computer networks Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Register-Transfer-Level Implementation Computer Communication Networks Processor Architectures |
| ISBN | 3-540-30102-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Address I -- Some Real Observations on Virtual Machines -- Session 1A: Cache and Memory -- Replica Victim Caching to Improve Reliability of In-Cache Replication -- Efficient Victim Mechanism on Sector Cache Organization -- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy -- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures -- Session 1B: Reconfigurable and Embedded Architectures -- A Configurable System-on-Chip Architecture for Embedded Devices -- An Auto-adaptative Reconfigurable Architecture for the Control -- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory -- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System -- Session 2A: Processor Architecture and Design I -- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP -- TengYue-1: A High Performance Embedded SoC -- A Fault-Tolerant Single-Chip Multiprocessor -- Session 2B: Power and Energy Management -- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy -- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization -- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption -- Session 3A: Processor Architecture and Design II -- Dynamic Reallocation of Functional Units in Superscalar Processors -- Multiple-Dimension Scalable Adaptive Stream Architecture -- Impact of Register-Cache Bandwidth Variation on Processor Performance -- Session 3B: Compiler and Operating System Issues -- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling -- Continuous Adaptive Object-Code Re-optimization Framework -- Initial Evaluation of a User-Level Device Driver Framework -- Keynote Address II -- A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? -- Session 4A: Application-Specific Systems -- A Cost-Effective Supersampling for Full Scene AntiAliasing -- A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) -- Scalable Design Framework for JPEG2000 System Architecture -- Real-Time Three Dimensional Vision -- Session 4B: Interconnection Networks -- A Router Architecture for QoS Capable Clusters -- Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability -- Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube -- A Two-Level On-Chip Bus System Based on Multiplexers -- Keynote Address III -- Make Computers Cheaper and Simpler -- Session 5A: Prediction Techniques -- A Low Power Branch Predictor to Selectively Access the BTB -- Static Techniques to Improve Power Efficiency of Branch Predictors -- Choice Predictor for Free -- Performance Impact of Different Data Value Predictors -- Session 5B: Parallel Architecture and Programming -- Heterogeneous Networks of Workstations -- Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays -- Order Independent Transparency for Image Composition Parallel Rendering Machines -- An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid Environments -- Session 6A: Microarchitecture Design and Evaluations -- Validating Word-Oriented Processors for Bit and Multi-word Operations -- Dynamic Fetch Engine for Simultaneous Multithreaded Processors -- A Novel Rename Register Architecture and Performance Analysis -- Session 6B: Memory and I/O Systems -- A New Hierarchy Cache Scheme Using RAM and Pagefile -- An Object-Oriented Data Storage System on Network-Attached Object Devices -- A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory -- Session 7A: Potpourri -- A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking -- A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel -- Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization. |
| Record Nr. | UNINA-9910144151503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CPU Design and Practice / / by Wenxiang Wang, Jinzhang Xing
| CPU Design and Practice / / by Wenxiang Wang, Jinzhang Xing |
| Autore | Wang Wenxiang |
| Edizione | [1st ed. 2025.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2025 |
| Descrizione fisica | 1 online resource (398 pages) |
| Disciplina | 004.22 |
| Altri autori (Persone) |
XingJinzhang
LuRongmin HaoMiao XuTianhao |
| Collana | Professional and Applied Computing Series |
| Soggetto topico |
Microprocessors
Computer architecture Computer hardware description languages Computers Processor Architectures Register-Transfer-Level Implementation Computer Hardware |
| ISBN | 981-9665-73-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Overview of the CPU Chip Development Process -- Chapter 2. Hardware Experiment Platform and FPGA Design Flow -- Chapter 3. Fundamentals of Digital Logic Circuit Design -- Chapter 4. Design A Single-cycle CPU -- Chapter 5. Design A Simple Pipelined CPU -- Chapter 6. AddMore User Mode Instructions into Pipeline -- Chapter 7. Support Exception and Interrupt -- Chapter 8. AXIBus Interface Design -- Chapter 9. Storage Management Unit Design -- Chapter 10. Cache Design -- Chapter 11. Advanced Experimental Environments -- Chapter 12. Advanced Design. |
| Record Nr. | UNINA-9911034958303321 |
Wang Wenxiang
|
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| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2025 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic and Applications. From FPGAs to Computing Paradigm : 8th International Workshop, FPL'98 Tallinn, Estonia, August 31 - September 3, 1998 Proceedings / / edited by Reiner W. Hartenstein, Andres Keevallik
| Field-Programmable Logic and Applications. From FPGAs to Computing Paradigm : 8th International Workshop, FPL'98 Tallinn, Estonia, August 31 - September 3, 1998 Proceedings / / edited by Reiner W. Hartenstein, Andres Keevallik |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
| Descrizione fisica | 1 online resource (XIII, 539 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer systems
Software engineering Artificial intelligence Logic design Computer arithmetic and logic units Computer hardware description languages Computer System Implementation Software Engineering Artificial Intelligence Logic Design Arithmetic and Logic Structures Register-Transfer-Level Implementation |
| ISBN | 3-540-68066-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
New CAD framework extends simulation of dynamically reconfigurable logic -- Pebble: A language for parametrised and reconfigurable hardware design -- Integrated development environment for logic synthesis based on dynamically reconfigurable FPGAs -- Designing for Xilinx XC6200 FPGAs -- Perspectives of reconfigurable computing in research, industry and education -- Field-programmable logic: Catalyst for new computing paradigms -- Run-time management of dynamically reconfigurable designs -- Acceleration of satisfiability algorithms by reconfigurable hardware -- An optimized design flow for fast FPGA-based rapid prototyping -- A knowledge-based system for prototyping on FPGAs -- JVX — A rapid prototyping system based on Java and FPGAs -- Prototyping new ILP architectures using FPGAs -- CAD system for ASM and FSM synthesis -- Fast floorplanning for FPGAs -- SRAM-based FPGAs: A fault model for the configurable logic modules -- Reconfigurable hardware as shared resource in multipurpose computers -- Reconfigurable computer array: The bridge between high speed sensors and low speed computing -- A reconfigurable engine for real-time video processing -- An FPGA implementation of a magnetic bearing controller for mechatronic applications -- Exploiting contemporary memory techniques in reconfigurable accelerators -- Self modifying circuitry — A platform for tractable virtual circuitry -- REACT: Reactive environment for runtime reconfiguration -- Evaluation of the XC6200-series architecture for cryptographic applications -- An FPGA-based object recognition machine -- PCI-SCI protocol translations: Applying microprogramming concepts to FPGAs -- Instruction-level parallelism for reconfigurable computing -- A hardware/software co-design environment for reconfigurable logic systems -- Mapping loops ontoreconfigurable architectures -- Speed optimization of the ALR circuit using an FPGA with embedded RAM: A design experience -- High-level synthesis for dynamically reconfigurable hardware/software systems -- Dynamic specialisation of XC6200 FPGAs by partial evaluation -- WebScope: A circuit debug tool -- Computing Goldbach partitions using pseudo-random bit generator operators on an FPGA systolic array -- Solving boolean satisfiability with dynamic hardware configurations -- Modular exponent realization on FPGAs -- Cost effective 2×2 inner product processors -- A field-programmable gate-array system for evolutionary computation -- A transmutable telecom system -- A survey of reconfigurable computing architectures -- A novel field programmable gate array architecture for high speed arithmetic processing -- Accelerating DTP with reconfigurable computing engines -- Hardware mapping of a parallel algorithm for matrix-vector multiplication overlapping communications and computations -- An interactive datasheet for the xilinx XC6200 -- Fast adaptive image processing in FPGAs using stack filters -- Increasing microprocessor performance with tightly-coupled reconfigurable logic arrays -- A high-performance computing module for a low earth orbit satellite using reconfigurable logic -- Maestro-link: A high performance interconnect for PC cluster -- A hardware implementation of Constraint Satisfaction Problem based on new reconfigurante LSI architecture -- A hardware operating system for dynamic reconfiguration of FPGAs -- High speed low level image processing on FPGAs using distributed arithmetic -- A flexible implementation of high-performance FIR filters on Xilinx FPGAs -- Implementing processor arrays on FPGAs -- Reconfigurable hardware — A study in codesign -- Statechart-based HW/SW-codesign of amulti-FPGA-board and a microprocessor -- Simulation of ATM switches using dynamically reconfigurable FPGA's -- Fast prototyping using system emulators -- Space-efficient mapping of 2D-DCT onto dynamically configurable coarse-grained architectures -- XILINX4000 architecture — Driven synthesis for speed -- The PLD-implementation of Boolean function characterized by minimum delay -- Reconfigurable PCI-BUS interface (RPCI) -- Programmable prototyping system for image processing -- A co-simulation concept for an efficient analysis of complex logic designs -- Programming and implementation of reconfigurable routers -- Virtual instruments based on reconfigurable logic -- The >S |
| Record Nr. | UNINA-9910143489103321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner
| Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner |
| Edizione | [1st ed. 1996.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 |
| Descrizione fisica | 1 online resource (X, 436 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Logic design Microprocessors Computational complexity Computer-aided engineering Electronics Microelectronics Computer System Implementation Logic Design Register-Transfer-Level Implementation Complexity Computer-Aided Engineering (CAD, CAE) and Design Electronics and Microelectronics, Instrumentation |
| ISBN | 3-540-70670-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Portable pipeline synthesis for FCCMs -- Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play? -- A framework for developing parametrised FPGA libraries -- FACT: Co-evaluation environment for FPGA architecture and CAD system -- An universal CLA adder generator for SRAM-based FPGAs -- An emulation system of the WASMII: A data driven computer on a virtual hardware -- Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view -- The design of a coprocessor board using Xilinx's XC6200 FPGA — An experience report -- RACE: Reconfigurable and adaptive computing environment -- Computing 2-D DFTs using FPGAs -- CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping -- Architectural synthesis and efficient circuit implementation for field programmable gate arrays -- RaPiD — Reconfigurable pipelined datapath -- Solving satisfiability problems on FPGAs -- FPGA implementation of the block-matching algorithm for motion estimation in image coding -- Parallel CRC computation in FPGAs -- Coherent demodulation with FPGAs -- The Trianus system and its application to custom computing -- Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form -- Flexible codesign target architecture for early prototyping of CMIST systems -- Attempt-1: A reconfigurable multiprocessor testbed -- A slow motion engine for the analysis of FPGA-based prototypes -- Implementing reconfigurable datapaths in FPGAs for adaptive filter design -- A fast constant coefficient multiplier for the XC6200 -- Key issues for user acceptance of FPGA design tools -- Reconfigurable DSP demonstrators for the development of spacecraft payload processors -- Reconfigurable logic based fibre channel network card with sub 2 ?s raw latency -- An asynchronous transfer mode (ATM) stream demultiplexer and switch -- Optically reconfigurable FPGAs: Is this a future trend? -- CCSimP — An instruction-level costum-configurable processor for FPLDs -- Architectural synthesis techniques for dynamically reconfigurable logic -- Fast reconfigurable crossbar switching in FPGAs -- Growable FPGA macro generator -- Architectural strategies for implementing an image processing algorithm on XC6000 FPGA -- A virtual hardware operating system for the Xilinx XC6200 -- An experimental programmable environment for prototyping digital circuits -- Migration from schematic-based designs to a VHDL synthesis environment -- ASIC design and FPGA design: A unified design methodology applied to different technologies -- FIR filtering with FPGAs using quadrature sigma-delta modulation encoding -- A new FPGA technology mapping approach by cluster merging -- An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions -- Convolutional error decoding with FPGAs -- Metastability characteristics testing for programmable logic design -- Implementing ?? modulator prototype designs on an FPGA -- Design of a VME parameterized library for FPGAs -- Development of a telephone answering machine in a lab — FPGAs in Education -- FPGA design migration: Some remarks -- Concurrent design of hardware/software dedicated systems -- The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators -- Computing weight distributions of binary linear block codes on a CCM. |
| Record Nr. | UNISA-996465857503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
FPGA EDA : Design Principles and Implementation / / by Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
| FPGA EDA : Design Principles and Implementation / / by Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu |
| Autore | Tu Kaihui |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (229 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Computer-aided engineering
Compilers (Computer programs) C++ (Computer program language) Open source software Computer science Computer hardware description languages Computer-Aided Engineering (CAD, CAE) and Design Compilers and Interpreters C++ Open Source Theory and Algorithms for Application Domains Register-Transfer-Level Implementation |
| ISBN | 981-9977-55-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Device(Chip Design) Modelling -- Design(Application Design) Modelling -- Power Analysis -- Performance(Timing) Analysis -- Area Analysis -- Semi-custom EDA -- High-Level Synthesis -- Logic Synthesis -- Physical Implementation -- Bitstream Configuration -- Summary and Outlook. |
| Record Nr. | UNINA-9910831011003321 |
|
Tu Kaihui
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| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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High-speed Serial Buses in Embedded Systems / / by Feng Zhang
| High-speed Serial Buses in Embedded Systems / / by Feng Zhang |
| Autore | Zhang Feng |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Singapore : , : Springer Singapore : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XII, 366 p. 313 illus., 109 illus. in color.) |
| Disciplina | 004.64 |
| Soggetto topico |
Electrical engineering
Electronics Microelectronics Electronic circuits Computer input-output equipment Microprocessors Logic design Communications Engineering, Networks Electronics and Microelectronics, Instrumentation Circuits and Systems Input/Output and Data Communications Register-Transfer-Level Implementation Logic Design |
| ISBN | 981-15-1868-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | The History and Development of Bus -- The High-Speed Data Transfer based on SERDES -- ADC/DAC Data Transfer Based on JESD204 Protocol -- The High-speed Communication Architecture in SRIO -- The High-speed Data Transfer based on PCIE -- The High-speed Data Transfer based on Aurora -- A High-speed Data Recording Scheme based on SATA Protocol -- The Communication Structure of CompactPCI Express -- The Communication Structure of VPX -- The Implementation and Application of FC Protocol -- The Implementation and Application of Infiniband Protocol -- Appendixes. |
| Record Nr. | UNINA-9910373896803321 |
|
Zhang Feng
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| Singapore : , : Springer Singapore : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / / edited by José L. Ayala, Delong Shang, Alex Yakovlev
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / / edited by José L. Ayala, Delong Shang, Alex Yakovlev |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (IX, 258 p. 150 illus.) |
| Disciplina | 004.24 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Electronic digital computers—Evaluation
Computer simulation Computer networks Computer hardware description languages Logic design Compilers (Computer programs) System Performance and Evaluation Computer Modelling Computer Communication Networks Register-Transfer-Level Implementation Logic Design Compilers and Interpreters |
| ISBN | 3-642-36157-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Sleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. |
| Record Nr. | UNISA-996465983903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Job Scheduling Strategies for Parallel Processing [[electronic resource] ] : IPPS/SPDP'98 Workshop, Orlando, Florida, USA, March 30, 1998 Proceedings / / edited by Dror G. Feitelson, Larry Rudolph
| Job Scheduling Strategies for Parallel Processing [[electronic resource] ] : IPPS/SPDP'98 Workshop, Orlando, Florida, USA, March 30, 1998 Proceedings / / edited by Dror G. Feitelson, Larry Rudolph |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
| Descrizione fisica | 1 online resource (X, 266 p.) |
| Disciplina | 005.4/3475 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Operating systems (Computers) Computer programming Algorithms Microprocessors Computer System Implementation Operating Systems Programming Techniques Algorithm Analysis and Problem Complexity Processor Architectures Register-Transfer-Level Implementation |
| ISBN | 3-540-68536-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Metrics and benchmarking for parallel job scheduling -- A comparative study of real workload traces and synthetic workload models for parallel job scheduling -- Lachesis: A job scheduler for the cray T3E -- A resource management architecture for metacomputing systems -- Implementing the combination of time sharing and space sharing on AP/Linux -- Job scheduling scheme for pure space sharing among rigid jobs -- Predicting application run times using historical information -- Job scheduling strategies for networks of workstations -- Probabilistic loop scheduling considering communication overhead -- Improving first-come-first-serve job scheduling by gang scheduling -- Expanding symmetric multiprocessor capability through gang scheduling -- Overhead analysis of preemptive gang scheduling -- Dynamic coscheduling on workstation clusters. |
| Record Nr. | UNISA-996466131503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Job Scheduling Strategies for Parallel Processing [[electronic resource] ] : IPPS/SPDP'98 Workshop, Orlando, Florida, USA, March 30, 1998 Proceedings / / edited by Dror G. Feitelson, Larry Rudolph
| Job Scheduling Strategies for Parallel Processing [[electronic resource] ] : IPPS/SPDP'98 Workshop, Orlando, Florida, USA, March 30, 1998 Proceedings / / edited by Dror G. Feitelson, Larry Rudolph |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
| Descrizione fisica | 1 online resource (X, 266 p.) |
| Disciplina | 005.4/3475 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer architecture
Operating systems (Computers) Computer programming Algorithms Microprocessors Computer System Implementation Operating Systems Programming Techniques Algorithm Analysis and Problem Complexity Processor Architectures Register-Transfer-Level Implementation |
| ISBN | 3-540-68536-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Metrics and benchmarking for parallel job scheduling -- A comparative study of real workload traces and synthetic workload models for parallel job scheduling -- Lachesis: A job scheduler for the cray T3E -- A resource management architecture for metacomputing systems -- Implementing the combination of time sharing and space sharing on AP/Linux -- Job scheduling scheme for pure space sharing among rigid jobs -- Predicting application run times using historical information -- Job scheduling strategies for networks of workstations -- Probabilistic loop scheduling considering communication overhead -- Improving first-come-first-serve job scheduling by gang scheduling -- Expanding symmetric multiprocessor capability through gang scheduling -- Overhead analysis of preemptive gang scheduling -- Dynamic coscheduling on workstation clusters. |
| Record Nr. | UNINA-9910143499303321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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