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ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
Autore Sloss Andrew N
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Descrizione fisica 1 online resource (703 p.)
Disciplina 005.1
Altri autori (Persone) SymesDominic
WrightChris <1953->
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico Computer software - Development
RISC microprocessors
Computer architecture
Soggetto genere / forma Electronic books.
ISBN 1-281-00723-4
9786611007232
0-08-049049-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions
4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling
6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal
8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy
12.4 Coprocessor 15 and Caches
Record Nr. UNINA-9910450501903321
Sloss Andrew N  
Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
Autore Sloss Andrew N
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Descrizione fisica 1 online resource (703 p.)
Disciplina 005.1
Altri autori (Persone) SymesDominic
WrightChris <1953->
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico Computer software - Development
RISC microprocessors
Computer architecture
ISBN 1-281-00723-4
9786611007232
0-08-049049-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions
4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling
6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal
8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy
12.4 Coprocessor 15 and Caches
Record Nr. UNINA-9910783135403321
Sloss Andrew N  
Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
Autore Sloss Andrew N
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Descrizione fisica 1 online resource (703 p.)
Disciplina 005.1
Altri autori (Persone) SymesDominic
WrightChris <1953->
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico Computer software - Development
RISC microprocessors
Computer architecture
ISBN 1-281-00723-4
9786611007232
0-08-049049-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions
4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling
6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal
8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy
12.4 Coprocessor 15 and Caches
Record Nr. UNINA-9910827091703321
Sloss Andrew N  
Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
AVR [[electronic resource] ] : an introductory course / / John Morton
AVR [[electronic resource] ] : an introductory course / / John Morton
Autore Morton John <1980->
Edizione [1st edition]
Pubbl/distr/stampa Oxford, : Newnes, 2002
Descrizione fisica 1 online resource (254 p.)
Disciplina 629.895416
Soggetto topico Programmable controllers
RISC microprocessors
Soggetto genere / forma Electronic books.
ISBN 1-281-03496-7
9786611034962
1-4356-0552-7
0-08-049972-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; AVR: An Introductory Course; Copyright Page; Contents; Acknowledgements; Preface; Chapter 1. Introduction; Short bit for PIC users; Number systems; Adding in binary; Negative numbers; An 8-bit Flash microcontroller; Initial steps; Choosing your model; Flowchart; Writing; Assembling; Registers; Instructions; Program template; Chapter 2. Basic Operations with AT90S1200 and Tiny12; Program A: LED on; Programs B and C: Push Button; Programs D and E: Counter; Program F: Chaser; Program G: Counter v.3.0; Program H: Traffic Lights; Program I: Logic Gate Simulator
Major Program J: Frequency Counter Chapter 3. Introducing the rest of the family; Chapter 4. Intermediate Operations; Interrupts; Program K: Reaction Tester; Program L: 4-bit analogue to digital converter; Program M: Voltage Inverter; Major Program N: Melody Maker; Chapter 5. Advanced Operations; PWM- Pulse Width Modulation; UART; Program O: Keyboard Converter; Final Program P: Computer Controlled Robot; Conclusions; Appendix A. Specifications for some PICs; Appendix B. Pin layouts of various AVRs; Appendix C. Instruction overview; Appendix D. Instruction glossary
Appendix E. Interrupt vector tablesAppendix G. ASCII conversion; Appendix H. When all else fails, read this; Appendix I. Contacts and further reading; Appendix J. Sample programs; Answers to exercises; Index
Record Nr. UNINA-9910457298003321
Morton John <1980->  
Oxford, : Newnes, 2002
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
AVR [[electronic resource] ] : an introductory course / / John Morton
AVR [[electronic resource] ] : an introductory course / / John Morton
Autore Morton John <1980->
Edizione [1st edition]
Pubbl/distr/stampa Oxford, : Newnes, 2002
Descrizione fisica 1 online resource (254 p.)
Disciplina 629.895416
Soggetto topico Programmable controllers
RISC microprocessors
ISBN 1-281-03496-7
9786611034962
1-4356-0552-7
0-08-049972-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; AVR: An Introductory Course; Copyright Page; Contents; Acknowledgements; Preface; Chapter 1. Introduction; Short bit for PIC users; Number systems; Adding in binary; Negative numbers; An 8-bit Flash microcontroller; Initial steps; Choosing your model; Flowchart; Writing; Assembling; Registers; Instructions; Program template; Chapter 2. Basic Operations with AT90S1200 and Tiny12; Program A: LED on; Programs B and C: Push Button; Programs D and E: Counter; Program F: Chaser; Program G: Counter v.3.0; Program H: Traffic Lights; Program I: Logic Gate Simulator
Major Program J: Frequency Counter Chapter 3. Introducing the rest of the family; Chapter 4. Intermediate Operations; Interrupts; Program K: Reaction Tester; Program L: 4-bit analogue to digital converter; Program M: Voltage Inverter; Major Program N: Melody Maker; Chapter 5. Advanced Operations; PWM- Pulse Width Modulation; UART; Program O: Keyboard Converter; Final Program P: Computer Controlled Robot; Conclusions; Appendix A. Specifications for some PICs; Appendix B. Pin layouts of various AVRs; Appendix C. Instruction overview; Appendix D. Instruction glossary
Appendix E. Interrupt vector tablesAppendix G. ASCII conversion; Appendix H. When all else fails, read this; Appendix I. Contacts and further reading; Appendix J. Sample programs; Answers to exercises; Index
Record Nr. UNINA-9910784342103321
Morton John <1980->  
Oxford, : Newnes, 2002
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
AVR : an introductory course / / John Morton
AVR : an introductory course / / John Morton
Autore Morton John <1980->
Edizione [1st edition]
Pubbl/distr/stampa Oxford, : Newnes, 2002
Descrizione fisica 1 online resource (254 p.)
Disciplina 629.895416
Soggetto topico Programmable controllers
RISC microprocessors
ISBN 1-281-03496-7
9786611034962
1-4356-0552-7
0-08-049972-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; AVR: An Introductory Course; Copyright Page; Contents; Acknowledgements; Preface; Chapter 1. Introduction; Short bit for PIC users; Number systems; Adding in binary; Negative numbers; An 8-bit Flash microcontroller; Initial steps; Choosing your model; Flowchart; Writing; Assembling; Registers; Instructions; Program template; Chapter 2. Basic Operations with AT90S1200 and Tiny12; Program A: LED on; Programs B and C: Push Button; Programs D and E: Counter; Program F: Chaser; Program G: Counter v.3.0; Program H: Traffic Lights; Program I: Logic Gate Simulator
Major Program J: Frequency Counter Chapter 3. Introducing the rest of the family; Chapter 4. Intermediate Operations; Interrupts; Program K: Reaction Tester; Program L: 4-bit analogue to digital converter; Program M: Voltage Inverter; Major Program N: Melody Maker; Chapter 5. Advanced Operations; PWM- Pulse Width Modulation; UART; Program O: Keyboard Converter; Final Program P: Computer Controlled Robot; Conclusions; Appendix A. Specifications for some PICs; Appendix B. Pin layouts of various AVRs; Appendix C. Instruction overview; Appendix D. Instruction glossary
Appendix E. Interrupt vector tablesAppendix G. ASCII conversion; Appendix H. When all else fails, read this; Appendix I. Contacts and further reading; Appendix J. Sample programs; Answers to exercises; Index
Altri titoli varianti Automatic voltage regulator : an introductory course
Record Nr. UNINA-9910825035303321
Morton John <1980->  
Oxford, : Newnes, 2002
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
See MIPS run [[electronic resource] /] / Dominic Sweetman
See MIPS run [[electronic resource] /] / Dominic Sweetman
Autore Sweetman Dominic
Edizione [2nd ed.]
Pubbl/distr/stampa San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
Descrizione fisica 1 online resource (513 p.)
Disciplina 004.165
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico MIPS (Computer architecture)
RISC microprocessors
Embedded computer systems - Programming
Soggetto genere / forma Electronic books.
ISBN 1-281-02320-5
9786611023201
0-08-052523-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; See MIPS® Run; Copyright Page; Foreword; Contents; Preface; Style and Limits; Conventions; Acknowledgments; Chapter 1. RISCs and MIPS Architectures; 1.1 Pipelines; 1.2 The MIPS Five-Stage Pipeline; 1.3 RISC and CISC; 1.4 Great MIPS Chips of the Past and Present; 1.5 MIPS Compared with CISC Architectures; Chapter 2. MIPS Architecture; 2.1 A Flavor of MIPS Assembly Language; 2.2 Registers; 2.3 Integer Multiply Unit and Registers; 2.4 Loading and Storing: Addressing Modes; 2.5 Data Types in Memory and Registers; 2.6 Synthesized Instructions in Assembly Language
2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space; 2.9 Pipeline Visibility; Chapter 3. Coprocessor 0: MIPS Processor Control; 3.1 CPU Control Instructions; 3.2 Which Registers Are RelevantWhen?; 3.3 CPU Control Registers and Their Encoding; 3.4 CP0 Hazards-A Trap for the Unwary; Chapter 4. How CachesWork on MIPS Processors; 4.1 Caches and Cache Management; 4.2 How CachesWork; 4.3 Write-Through Caches in Early MIPS CPUs; 4.4 Write-Back Caches in MIPS CPUs; 4.5 Other Choices in Cache Design; 4.6 Managing Caches; 4.7 L2 and L3 Caches
4.8 Cache Configurations for MIPS CPUs4.9 Programming MIPS32/64 Caches; 4.10 Cache Efficiency; 4.11 Reorganizing Software to Influence Cache Efficiency; 4.12 Cache Aliases; Chapter 5. Exceptions, Interrupts, and Initialization; 5.1 Precise Exceptions; 5.2 When Exceptions Happen; 5.3 Exception Vectors:Where Exception Handling Starts; 5.4 Exception Handling: Basics; 5.5 Returning from an Exception; 5.6 Nesting Exceptions; 5.7 An Exception Routine; 5.8 Interrupts; 5.9 Starting Up; 5.10 Emulating Instructions; Chapter 6. Low-level Memory Management and the TLB
6.1 The TLB/MMU Hardware andWhat It Does6.2 TLB/MMU Registers Described; 6.3 TLB/MMU Control Instructions; 6.4 Programming the TLB; 6.5 Hardware-Friendly Page Tables and Refill Mechanism; 6.6 Everyday Use of the MIPS TLB; 6.7 Memory Management in a Simpler OS; Chapter 7. Floating-Point Support; 7.1 A Basic Description of Floating Point; 7.2 The IEEE 754 Standard and Its Background; 7.3 How IEEE Floating-Point Numbers Are Stored; 7.4 MIPS Implementation of IEEE 754; 7.5 Floating-Point Registers; 7.6 Floating-Point Exceptions/Interrupts; 7.7 Floating-Point Control: The Control/Status Register
7.8 Floating-Point Implementation Register7.9 Guide to FP Instructions; 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE; 7.11 Instruction Timing Requirements; 7.12 Instruction Timing for Speed; 7.13 Initialization and Enabling on Demand; 7.14 Floating-Point Emulation; Chapter 8. Complete Guide to the MIPS Instruction Set; 8.1 A Simple Example; 8.2 Assembly Instructions andWhat They Mean; 8.3 Floating-Point Instructions; 8.4 Differences in MIPS32/64 Release 1; 8.5 Peculiar Instructions and Their Purposes; 8.6 Instruction Encodings; 8.7 Instructions by Functional Group
Chapter 9. Reading MIPS Assembly Language
Record Nr. UNINA-9910458480803321
Sweetman Dominic  
San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
See MIPS run [[electronic resource] /] / Dominic Sweetman
See MIPS run [[electronic resource] /] / Dominic Sweetman
Autore Sweetman Dominic
Edizione [2nd ed.]
Pubbl/distr/stampa San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
Descrizione fisica 1 online resource (513 p.)
Disciplina 004.165
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico MIPS (Computer architecture)
RISC microprocessors
Embedded computer systems - Programming
ISBN 1-281-02320-5
9786611023201
0-08-052523-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; See MIPS® Run; Copyright Page; Foreword; Contents; Preface; Style and Limits; Conventions; Acknowledgments; Chapter 1. RISCs and MIPS Architectures; 1.1 Pipelines; 1.2 The MIPS Five-Stage Pipeline; 1.3 RISC and CISC; 1.4 Great MIPS Chips of the Past and Present; 1.5 MIPS Compared with CISC Architectures; Chapter 2. MIPS Architecture; 2.1 A Flavor of MIPS Assembly Language; 2.2 Registers; 2.3 Integer Multiply Unit and Registers; 2.4 Loading and Storing: Addressing Modes; 2.5 Data Types in Memory and Registers; 2.6 Synthesized Instructions in Assembly Language
2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space; 2.9 Pipeline Visibility; Chapter 3. Coprocessor 0: MIPS Processor Control; 3.1 CPU Control Instructions; 3.2 Which Registers Are RelevantWhen?; 3.3 CPU Control Registers and Their Encoding; 3.4 CP0 Hazards-A Trap for the Unwary; Chapter 4. How CachesWork on MIPS Processors; 4.1 Caches and Cache Management; 4.2 How CachesWork; 4.3 Write-Through Caches in Early MIPS CPUs; 4.4 Write-Back Caches in MIPS CPUs; 4.5 Other Choices in Cache Design; 4.6 Managing Caches; 4.7 L2 and L3 Caches
4.8 Cache Configurations for MIPS CPUs4.9 Programming MIPS32/64 Caches; 4.10 Cache Efficiency; 4.11 Reorganizing Software to Influence Cache Efficiency; 4.12 Cache Aliases; Chapter 5. Exceptions, Interrupts, and Initialization; 5.1 Precise Exceptions; 5.2 When Exceptions Happen; 5.3 Exception Vectors:Where Exception Handling Starts; 5.4 Exception Handling: Basics; 5.5 Returning from an Exception; 5.6 Nesting Exceptions; 5.7 An Exception Routine; 5.8 Interrupts; 5.9 Starting Up; 5.10 Emulating Instructions; Chapter 6. Low-level Memory Management and the TLB
6.1 The TLB/MMU Hardware andWhat It Does6.2 TLB/MMU Registers Described; 6.3 TLB/MMU Control Instructions; 6.4 Programming the TLB; 6.5 Hardware-Friendly Page Tables and Refill Mechanism; 6.6 Everyday Use of the MIPS TLB; 6.7 Memory Management in a Simpler OS; Chapter 7. Floating-Point Support; 7.1 A Basic Description of Floating Point; 7.2 The IEEE 754 Standard and Its Background; 7.3 How IEEE Floating-Point Numbers Are Stored; 7.4 MIPS Implementation of IEEE 754; 7.5 Floating-Point Registers; 7.6 Floating-Point Exceptions/Interrupts; 7.7 Floating-Point Control: The Control/Status Register
7.8 Floating-Point Implementation Register7.9 Guide to FP Instructions; 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE; 7.11 Instruction Timing Requirements; 7.12 Instruction Timing for Speed; 7.13 Initialization and Enabling on Demand; 7.14 Floating-Point Emulation; Chapter 8. Complete Guide to the MIPS Instruction Set; 8.1 A Simple Example; 8.2 Assembly Instructions andWhat They Mean; 8.3 Floating-Point Instructions; 8.4 Differences in MIPS32/64 Release 1; 8.5 Peculiar Instructions and Their Purposes; 8.6 Instruction Encodings; 8.7 Instructions by Functional Group
Chapter 9. Reading MIPS Assembly Language
Record Nr. UNINA-9910784549403321
Sweetman Dominic  
San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
See MIPS run [[electronic resource] /] / Dominic Sweetman
See MIPS run [[electronic resource] /] / Dominic Sweetman
Autore Sweetman Dominic
Edizione [2nd ed.]
Pubbl/distr/stampa San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
Descrizione fisica 1 online resource (513 p.)
Disciplina 004.165
Collana The Morgan Kaufmann Series in Computer Architecture and Design
Soggetto topico MIPS (Computer architecture)
RISC microprocessors
Embedded computer systems - Programming
ISBN 1-281-02320-5
9786611023201
0-08-052523-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; See MIPS® Run; Copyright Page; Foreword; Contents; Preface; Style and Limits; Conventions; Acknowledgments; Chapter 1. RISCs and MIPS Architectures; 1.1 Pipelines; 1.2 The MIPS Five-Stage Pipeline; 1.3 RISC and CISC; 1.4 Great MIPS Chips of the Past and Present; 1.5 MIPS Compared with CISC Architectures; Chapter 2. MIPS Architecture; 2.1 A Flavor of MIPS Assembly Language; 2.2 Registers; 2.3 Integer Multiply Unit and Registers; 2.4 Loading and Storing: Addressing Modes; 2.5 Data Types in Memory and Registers; 2.6 Synthesized Instructions in Assembly Language
2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space; 2.9 Pipeline Visibility; Chapter 3. Coprocessor 0: MIPS Processor Control; 3.1 CPU Control Instructions; 3.2 Which Registers Are RelevantWhen?; 3.3 CPU Control Registers and Their Encoding; 3.4 CP0 Hazards-A Trap for the Unwary; Chapter 4. How CachesWork on MIPS Processors; 4.1 Caches and Cache Management; 4.2 How CachesWork; 4.3 Write-Through Caches in Early MIPS CPUs; 4.4 Write-Back Caches in MIPS CPUs; 4.5 Other Choices in Cache Design; 4.6 Managing Caches; 4.7 L2 and L3 Caches
4.8 Cache Configurations for MIPS CPUs4.9 Programming MIPS32/64 Caches; 4.10 Cache Efficiency; 4.11 Reorganizing Software to Influence Cache Efficiency; 4.12 Cache Aliases; Chapter 5. Exceptions, Interrupts, and Initialization; 5.1 Precise Exceptions; 5.2 When Exceptions Happen; 5.3 Exception Vectors:Where Exception Handling Starts; 5.4 Exception Handling: Basics; 5.5 Returning from an Exception; 5.6 Nesting Exceptions; 5.7 An Exception Routine; 5.8 Interrupts; 5.9 Starting Up; 5.10 Emulating Instructions; Chapter 6. Low-level Memory Management and the TLB
6.1 The TLB/MMU Hardware andWhat It Does6.2 TLB/MMU Registers Described; 6.3 TLB/MMU Control Instructions; 6.4 Programming the TLB; 6.5 Hardware-Friendly Page Tables and Refill Mechanism; 6.6 Everyday Use of the MIPS TLB; 6.7 Memory Management in a Simpler OS; Chapter 7. Floating-Point Support; 7.1 A Basic Description of Floating Point; 7.2 The IEEE 754 Standard and Its Background; 7.3 How IEEE Floating-Point Numbers Are Stored; 7.4 MIPS Implementation of IEEE 754; 7.5 Floating-Point Registers; 7.6 Floating-Point Exceptions/Interrupts; 7.7 Floating-Point Control: The Control/Status Register
7.8 Floating-Point Implementation Register7.9 Guide to FP Instructions; 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE; 7.11 Instruction Timing Requirements; 7.12 Instruction Timing for Speed; 7.13 Initialization and Enabling on Demand; 7.14 Floating-Point Emulation; Chapter 8. Complete Guide to the MIPS Instruction Set; 8.1 A Simple Example; 8.2 Assembly Instructions andWhat They Mean; 8.3 Floating-Point Instructions; 8.4 Differences in MIPS32/64 Release 1; 8.5 Peculiar Instructions and Their Purposes; 8.6 Instruction Encodings; 8.7 Instructions by Functional Group
Chapter 9. Reading MIPS Assembly Language
Record Nr. UNINA-9910826308303321
Sweetman Dominic  
San Francisco, Calif., : Morgan Kaufmann Publishers/Elsevier, c2007
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