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3D Interconnect Architectures for Heterogeneous Technologies : Modeling and Optimization / / by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck
| 3D Interconnect Architectures for Heterogeneous Technologies : Modeling and Optimization / / by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck |
| Autore | Bamberg Lennart |
| Edizione | [1st ed. 2022.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022 |
| Descrizione fisica | 1 online resource (403 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Processor Architectures |
| ISBN | 3-030-98229-7 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I Introduction -- 1 Introduction to 3D Technologies -- 1.1 Motivation for Heterogenous 3D ICs -- 1.2 3D Technologies -- 1.3 TSV Capacitances—A Problem Resistant to Scaling -- 1.4 Conclusion -- 2 Interconnect Architectures for 3D Technologies -- 2.1 Interconnect Architectures -- 2.2 Overview of Interconnect Architectures for 3D ICs -- 2.3 Three-dimensional Networks on chips -- 2.4 Conclusion -- Part II 3D Technology Modeling -- 3 Power and Performance Formulas -- 3.1 High-Level Formula for the Power Consumption -- 3.2 High-Level Formula for the Propagation Delay -- 3.3 Matrix Formulations -- 3.4 Evaluation -- 3.5 Conclusion -- 4 Capacitance Estimation -- 4.1 Existing Capacitance Models -- 4.2 Edge and MOS Effects on the TSV Capacitances -- 4.3 TSV Capacitance Model -- 4.4 Evaluation -- 4.5 Conclusion -- Part III System Modeling -- xiii -- xiv Contents -- 5 Application and Simulation Models -- 5.1 Overview of the Modeling Approach -- 5.2 Application Traffic Model -- 5.3 Simulation Model of 3D NoCs -- 5.4 Simulator Interfaces -- 5.5 Conclusion -- 6 Bit-level Statistics -- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for -- Single Data Streams -- 6.2 Data-Stream Multiplexing -- 6.3 Bit-Level Statistics with Data-Stream Multiplexing -- 6.4 Evaluation -- 6.5 Conclusion -- 7 Ratatoskr Framework -- 7.1 Ratatoskr for Practitioners -- 7.2 Implementation -- 7.3 Evaluation -- 7.4 Case Study: Link Power Estimation and Optimization -- 7.5 Conclusion -- Part IV 3D-Interconnect Optimization -- 8 Low-Power Technique for 3D Interconnects -- 8.1 Fundamental Idea -- 8.2 Power-Optimal TSV assignment -- 8.3 Systematic Net-to-TSV Assignments -- 8.4 Combination with Traditional Low-Power Codes -- 8.5 Evaluation -- 8.6 Conclusion -- 9 Low-Power Technique for High-Performance 3D -- Interconnects. -- 9.1 Edge-Effect-Aware Crosstalk Classification -- 9.2 Existing Approaches and Their Limitations -- 9.3 Proposed Technique -- 9.4 Extension to a Low-Power3D CAC -- 9.5 Evaluation -- 9.6 Conclusion -- 10 Low-Power Technique for High-Performance 3D -- Interconnects (Misaligned) -- 10.1 Temporal-Misalignment Effect on the Crosstalk -- 10.2 Exploiting Misalignment to Improve the Performance -- 10.3 Effect on the TSV Power Consumption -- Contents xv -- 10.4 Evaluation -- 10.5 Conclusion -- 11 Low-Power Technique for Yield-Enhanced 3D Interconnects -- 11.1 Existing TSV Yield-Enhancement Techniques -- 11.2 Preliminaries—Logical Impact of TSV Faults -- 11.3 Fundamental Idea -- 11.4 Formal Problem Description -- 11.5 TSV Redundancy Schemes -- 11.6 Evaluation -- 11.7 Case Study -- 11.8 Conclusion -- Part V NoC Optimization for Heterogeneous 3D Integration -- 12 Heterogeneous Buffering for 3D NoCs251 -- 12.1 Buffer Distributions and Depths -- 12.2 Routers with Optimized Buffer Distribution -- 12.3 Routers with Optimized Buffer Depths -- 12.4 Evaluation -- 12.5 Discussion -- 12.6 Conclusion -- 13 Heterogeneous Routing for 3D NoCs -- 13.1 Heterogeneity and Routing -- 13.2 Modeling Heterogeneous Technologies -- 13.3 Modeling Communication -- 13.4 Routing Limitations from Heterogeneity -- 13.5 Heterogeneous Routing Algorithms -- 13.6 Heterogeneous Router Architectures -- 13.7 Low-Power Routing in Heterogeneous 3D ICs -- 13.8 Evaluation -- 13.9 Discussion -- 13.10Conclusion -- 14 Heterogeneous Virtualisation for 3D NoCs -- 14.1 Problem Description -- 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance -- 14.3 Evaluation -- 14.4 Conclusion -- 15 Network Synthesis and SoC Floor Planning -- 15.1 Fundamental Idea -- 15.2 Modelling and Optimization -- 15.3 Mixed-Integer Linear Program -- 15.4 Heuristic Solution -- xvi Contents -- 15.5 Evaluation -- 15.6 Conclusion -- Part VI Finale -- 16 Conclusion -- 16.1 Putting it all together -- 16.2 Impact on Future Work -- A Appendix -- B Pseudo Codes -- C Method to Calculate the Depletion-Region Widths -- D Modeling Logical OR Relations. |
| Record Nr. | UNINA-9910735388803321 |
Bamberg Lennart
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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3D Stacked Chips : From Emerging Processes to Heterogeneous Systems / / edited by Ibrahim (Abe) M. Elfadel, Gerhard Fettweis
| 3D Stacked Chips : From Emerging Processes to Heterogeneous Systems / / edited by Ibrahim (Abe) M. Elfadel, Gerhard Fettweis |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (XXIII, 339 p. 238 illus., 157 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronic Circuits and Systems Processor Architectures |
| ISBN | 3-319-20481-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Electrical 3D Integration -- Copper-based TSV – Interposer -- Multi-TSV Crosstalk Channel Equalization with Non-Uniform Quantization -- Energy Efficient Electrical Intra-Chip Stack Communication -- Clock Generators for Heterogeneous MPSoCs within 3D Chip Stacks -- Energy Efficient Communications Employing 1-Bit Quantization at the Receiver -- 2-nm Laser Synthesized Si-Nanoparticles for Low Power Memory Applications -- Accurate Temperature Measurement for 3D Thermal Management -- EDA Environments for 3D Chip Stacks -- Integrating 3D Floorplanning and Optimization of Thermal Through-Silicon Vias -- Introduction to Optical Inter- and Intraconnects -- Optical Through-Silicon Vias -- Integrated Optical Devices for 3D Photonic Transceivers -- Cantilever Design for Tunable WDM Filters based on Silicon Microring Resonators -- Athermal photonic circuits for optical on-chip interconnects -- Integrated Circuits for 3D Photonic Transceivers -- Review of interdigitated back contacted full heterojunction solar cell (IBC-SHJ): a simulation approach.-. |
| Record Nr. | UNINA-9910254242703321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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5G and E-Band Communication Circuits in Deep-Scaled CMOS / / by Marco Vigilante, Patrick Reynaert
| 5G and E-Band Communication Circuits in Deep-Scaled CMOS / / by Marco Vigilante, Patrick Reynaert |
| Autore | Vigilante Marco |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (205 pages) : illustrations |
| Disciplina | 004.16 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Electronic circuits
Microprocessors Circuits and Systems Electronic Circuits and Devices Processor Architectures |
| ISBN | 3-319-72646-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Gm Stage and Passives in deep-scaled CMOS -- Gain-Bandwidth Enhancement Techniques for mm-Wave fully integrated Amplifiers -- mm-Wave LC VCOs -- mm-Wave Dividers -- mm-Wave Broadband Downconverters -- mm-Wave Highly-Linear Broadband Power Amplifiers -- Conclusion. |
| Record Nr. | UNINA-9910299955203321 |
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Vigilante Marco
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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8051 Microcontrollers : Fundamental Concepts, Hardware, Software and Applications in Electronics / / by Salvador Pinillos Gimenez
| 8051 Microcontrollers : Fundamental Concepts, Hardware, Software and Applications in Electronics / / by Salvador Pinillos Gimenez |
| Autore | Gimenez Salvador Pinillos |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 322 p. 172 illus., 47 illus. in color.) |
| Disciplina | 004.165 |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Microprocessors Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures |
| ISBN | 3-319-76439-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Fundamental Concepts of Computer Systems -- 8051 Core Microcontrollers -- 8051 - Core Microcontroller Instruction Set -- Flowchart and Assembly Programming -- Subroutine and Structuring of the Assembly Programming Language -- Input/output Ports of 8051 - Core Microcontrollers -- Basic 8051 - Core Microcontroller Interruptions -- Timers/Counters of the 8051 Core Microcontroller -- The Serial Communication Interface of the 8051 - Core Microcontroller. |
| Record Nr. | UNINA-9910337654803321 |
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Gimenez Salvador Pinillos
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Active Object Languages: Current Research Trends / / edited by Frank de Boer, Ferruccio Damiani, Reiner Hähnle, Einar Broch Johnsen, Eduard Kamburjan
| Active Object Languages: Current Research Trends / / edited by Frank de Boer, Ferruccio Damiani, Reiner Hähnle, Einar Broch Johnsen, Eduard Kamburjan |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (382 pages) |
| Disciplina | 005.4 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer programming
Microprogramming Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Programming Techniques Control Structures and Microprogramming Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures |
| ISBN | 3-031-51060-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Active Objects based on Algebraic Effects -- Actor-based Designs for Distributed Self-organisation Programming -- Encore: Coda -- Bridging Between Active Objects: Multitier Programming for Distributed, Concurrent Systems -- A Survey of Actor-Like Programming Models for Serverless Computing -- Programming Language Implementations with Multiparty Session Types -- Modelling -- Integrated Timed Architectural Modeling/Execution Language -- Simulating User Journeys with Active Objects -- Actors Upgraded for Variability, Adaptability, and Determinism -- Analysis -- Integrating Data Privacy Compliance in Active Object Languages -- Context-aware Trace Contracts -- Type-Based Verification of Delegated Control in Hybrid Systems -- Enforced Dependencies for Active Objects. |
| Record Nr. | UNINA-9910806197803321 |
| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling : From the Clock Path to the Data Path / / by Saurabh Jain, Longyang Lin, Massimo Alioto
| Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling : From the Clock Path to the Data Path / / by Saurabh Jain, Longyang Lin, Massimo Alioto |
| Autore | Jain Saurabh |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XVI, 168 p. 113 illus., 107 illus. in color.) |
| Disciplina | 621.381 |
| Soggetto topico |
Electronic circuits
Computer engineering Internet of things Embedded computer systems Microprocessors Circuits and Systems Cyber-physical systems, IoT Processor Architectures |
| ISBN | 3-030-38796-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion. |
| Record Nr. | UNINA-9910377818103321 |
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Jain Saurabh
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Adaptive Processing of Sequences and Data Structures [[electronic resource] ] : International Summer School on Neural Networks, "E.R. Caianiello", Vietri sul Mare, Salerno, Italy, September 6-13, 1997, Tutorial Lectures / / edited by C.Lee Giles, Marco Gori
| Adaptive Processing of Sequences and Data Structures [[electronic resource] ] : International Summer School on Neural Networks, "E.R. Caianiello", Vietri sul Mare, Salerno, Italy, September 6-13, 1997, Tutorial Lectures / / edited by C.Lee Giles, Marco Gori |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
| Descrizione fisica | 1 online resource (XIV, 438 p.) |
| Disciplina | 006.3/2 |
| Collana | Lecture Notes in Artificial Intelligence |
| Soggetto topico |
Architecture, Computer
Computer programming Artificial intelligence Computers Microprocessors Data structures (Computer science) Computer System Implementation Programming Techniques Artificial Intelligence Computation by Abstract Devices Processor Architectures Data Structures |
| ISBN | 3-540-69752-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Recurrent neural network architectures: An overview -- Gradient based learning methods -- Diagrammatic methods for deriving and relating temporal neural network algorithms -- An introduction to learning structured information -- Neural networks for processing data structures -- The loading problem: Topics in complexity -- Learning dynamic Bayesian networks -- Probabilistic models of neuronal spike trains -- Temporal models in blind source separation -- Recursive neural networks and automata -- The neural network pushdown automaton: Architecture, dynamics and training -- Neural dynamics with stochasticity -- Parsing the stream of time: The value of event-based segmentation in a complex real-world control problem -- Hybrid HMM/ANN systems for speech recognition: Overview and new research directions -- Predictive models for sequence modelling, application to speech and character recognition. |
| Record Nr. | UNISA-996466108403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Adaptive Processing of Sequences and Data Structures : International Summer School on Neural Networks, "E.R. Caianiello", Vietri sul Mare, Salerno, Italy, September 6-13, 1997, Tutorial Lectures / / edited by C.Lee Giles, Marco Gori
| Adaptive Processing of Sequences and Data Structures : International Summer School on Neural Networks, "E.R. Caianiello", Vietri sul Mare, Salerno, Italy, September 6-13, 1997, Tutorial Lectures / / edited by C.Lee Giles, Marco Gori |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
| Descrizione fisica | 1 online resource (XIV, 438 p.) |
| Disciplina | 006.3/2 |
| Collana | Lecture Notes in Artificial Intelligence |
| Soggetto topico |
Computer architecture
Computer programming Artificial intelligence Computers Microprocessors Data structures (Computer science) Computer System Implementation Programming Techniques Artificial Intelligence Computation by Abstract Devices Processor Architectures Data Structures |
| ISBN | 3-540-69752-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Recurrent neural network architectures: An overview -- Gradient based learning methods -- Diagrammatic methods for deriving and relating temporal neural network algorithms -- An introduction to learning structured information -- Neural networks for processing data structures -- The loading problem: Topics in complexity -- Learning dynamic Bayesian networks -- Probabilistic models of neuronal spike trains -- Temporal models in blind source separation -- Recursive neural networks and automata -- The neural network pushdown automaton: Architecture, dynamics and training -- Neural dynamics with stochasticity -- Parsing the stream of time: The value of event-based segmentation in a complex real-world control problem -- Hybrid HMM/ANN systems for speech recognition: Overview and new research directions -- Predictive models for sequence modelling, application to speech and character recognition. |
| Record Nr. | UNINA-9910143453603321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Advanced Computer Architecture : 13th Conference, ACA 2020, Kunming, China, August 13–15, 2020, Proceedings / / edited by Dezun Dong, Xiaoli Gong, Cunlu Li, Dongsheng Li, Junjie Wu
| Advanced Computer Architecture : 13th Conference, ACA 2020, Kunming, China, August 13–15, 2020, Proceedings / / edited by Dezun Dong, Xiaoli Gong, Cunlu Li, Dongsheng Li, Junjie Wu |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XIII, 336 p. 204 illus., 154 illus. in color.) |
| Disciplina | 005.3 |
| Collana | Communications in Computer and Information Science |
| Soggetto topico |
Microprocessors
Computer architecture Computer networks Computer systems Application software Operating systems (Computers) Microprogramming Processor Architectures Computer Communication Networks Computer System Implementation Computer and Information Systems Applications Operating Systems Control Structures and Microprogramming |
| ISBN | 981-15-8135-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Interconnection network, Router and Network Interface Architecture -- Accelerator-based, Application-specific and Reconfigurable Architecture -- Processor, Memory, and Storage Systems Architecture -- Model, Simulation and Evaluation of Architecture -- New Trends of Technologies and Applications. |
| Record Nr. | UNINA-9910427719803321 |
| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Advanced Computer Architecture : 12th Conference, ACA 2018, Yingkou, China, August 10-11, 2018, Proceedings / / edited by Chao Li, Junjie Wu
| Advanced Computer Architecture : 12th Conference, ACA 2018, Yingkou, China, August 10-11, 2018, Proceedings / / edited by Chao Li, Junjie Wu |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (X, 233 p. 126 illus.) |
| Disciplina | 004 |
| Collana | Communications in Computer and Information Science |
| Soggetto topico |
Microprocessors
Computer architecture Computers, Special purpose Computer systems Operating systems (Computers) Logic design Processor Architectures Special Purpose and Application-Based Systems Computer System Implementation Operating Systems Logic Design |
| ISBN | 981-13-2423-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910299298003321 |
| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Soggetto topico
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Processor Architectures
(711)
- Microprocessors (708)
- Computer architecture (326)
- Electronic circuits (252)
- Computer System Implementation (179)