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Issues and practices [[electronic resource] /] / edited by Patrick Crowley ... [et al.]
| Issues and practices [[electronic resource] /] / edited by Patrick Crowley ... [et al.] |
| Pubbl/distr/stampa | San Francisco, : Morgan Kaufmann, 2005 |
| Descrizione fisica | 1 online resource (335 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) | CrowleyPatrick |
| Collana | Network processor design |
| Soggetto topico |
Network processors - Design
Application-specific integrated circuits - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-62622-4
9786610626229 0-08-051250-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Network Processor Design Issues and Practices; Copyright Page; About the Editors; Contents; Preface; Chapter 1. Network Processors: New Horizons; 1.1 Architecture; 1.2 Tools and Techniques; 1.3 Applications; 1.4 Conclusions; References; Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches; 2.1 Instruction Delivery in NP Data Processors; 2.2 Segmented Instruction Cache; 2.3 Experimental Evaluation; 2.4 Related Work; 2.5 Conclusions and Future Work; References; Chapter 3. Efficient Packet Classification with Digest Caches
3.1 Related Work3.2 Our Approach; 3.3 Evaluation; 3.4 Hardware Overhead; 3.5 Conclusions; Acknowledgments; References; Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express; 4.1 Interface Fundamentals and Comparison; 4.2 Modeling the Interfaces; 4.3 Architecture Evaluation; 4.4 Conclusions; Acknowledgments; References; Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet; 5.1 Requirements on TCP Offload Solution; 5.2 Architecture of TOE Solution; 5.3 Performance Analysis; 5.4 Conclusions; Acknowledgments; References Chapter 6. A Hardware Platform for Network Intrusion Detection and Prevention6.1 Design Rationales and Principles; 6.2 Prototype NNIDS on a Network Interface; 6.3 Evaluation and Results; 6.4 Conclusions; References; Chapter 7. Packet Processing on a SIMD Stream Processor; 7.1 Background: Stream Programs and Architectures; 7.2 AES Encryption; 7.3 IPv4 Forwarding; 7.4 Related Work; 7.5 Conclusions and Future Work; Acknowledgments; References; Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations; 8.1 Problem Domain 8.2 Shangri-La. A Programming Environment for Packet-Processing Systems 1508.3 Design Details and Challenges; 8.4 Conclusions; References; Chapter 9. RNOS-A Middleware Platform for Low-Cost Packet-Processing Devices; 9.1 Scenario; 9.2 Analysis Model of RNOS; 9.3 Implementation Model of RNOS; 9.4 Measurements and Comparison; 9.5 Conclusions and Outlook; Acknowledgments; References; Chapter 10. On the Feasibility of Using Network Processors for DNA Queries; 10.1 Architecture; 10.2 Implementation Details; 10.3 Results; 10.4 Related Work; 10.5 Conclusions; Acknowledgments; References Chapter 11. Pipeline Task Scheduling on Network Processors11.1 The Pipeline Task Assignment Problem; 11.2 The Greedypipe Algorithm; 11.3 Pipeline Design with Greedypipe; 11.4 A Network Processor Problem; 11.5 Conclusions; Acknowledgments; References; Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs; 12.1 Related Work; 12.2 Modeling Packet-Processing Systems; 12.3 Scheduling; 12.4 Mapping the Application to the System; 12.5 Estimating the Resource Consumption; 12.6 A Design Space Exploration Example; 12.7 Conclusions Acknowledgments |
| Record Nr. | UNINA-9910458468403321 |
| San Francisco, : Morgan Kaufmann, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Issues and practices [[electronic resource] /] / edited by Patrick Crowley ... [et al.]
| Issues and practices [[electronic resource] /] / edited by Patrick Crowley ... [et al.] |
| Pubbl/distr/stampa | San Francisco, : Morgan Kaufmann, 2005 |
| Descrizione fisica | 1 online resource (335 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) | CrowleyPatrick |
| Collana | Network processor design |
| Soggetto topico |
Network processors - Design
Application-specific integrated circuits - Design |
| ISBN |
1-280-62622-4
9786610626229 0-08-051250-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Network Processor Design Issues and Practices; Copyright Page; About the Editors; Contents; Preface; Chapter 1. Network Processors: New Horizons; 1.1 Architecture; 1.2 Tools and Techniques; 1.3 Applications; 1.4 Conclusions; References; Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches; 2.1 Instruction Delivery in NP Data Processors; 2.2 Segmented Instruction Cache; 2.3 Experimental Evaluation; 2.4 Related Work; 2.5 Conclusions and Future Work; References; Chapter 3. Efficient Packet Classification with Digest Caches
3.1 Related Work3.2 Our Approach; 3.3 Evaluation; 3.4 Hardware Overhead; 3.5 Conclusions; Acknowledgments; References; Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express; 4.1 Interface Fundamentals and Comparison; 4.2 Modeling the Interfaces; 4.3 Architecture Evaluation; 4.4 Conclusions; Acknowledgments; References; Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet; 5.1 Requirements on TCP Offload Solution; 5.2 Architecture of TOE Solution; 5.3 Performance Analysis; 5.4 Conclusions; Acknowledgments; References Chapter 6. A Hardware Platform for Network Intrusion Detection and Prevention6.1 Design Rationales and Principles; 6.2 Prototype NNIDS on a Network Interface; 6.3 Evaluation and Results; 6.4 Conclusions; References; Chapter 7. Packet Processing on a SIMD Stream Processor; 7.1 Background: Stream Programs and Architectures; 7.2 AES Encryption; 7.3 IPv4 Forwarding; 7.4 Related Work; 7.5 Conclusions and Future Work; Acknowledgments; References; Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations; 8.1 Problem Domain 8.2 Shangri-La. A Programming Environment for Packet-Processing Systems 1508.3 Design Details and Challenges; 8.4 Conclusions; References; Chapter 9. RNOS-A Middleware Platform for Low-Cost Packet-Processing Devices; 9.1 Scenario; 9.2 Analysis Model of RNOS; 9.3 Implementation Model of RNOS; 9.4 Measurements and Comparison; 9.5 Conclusions and Outlook; Acknowledgments; References; Chapter 10. On the Feasibility of Using Network Processors for DNA Queries; 10.1 Architecture; 10.2 Implementation Details; 10.3 Results; 10.4 Related Work; 10.5 Conclusions; Acknowledgments; References Chapter 11. Pipeline Task Scheduling on Network Processors11.1 The Pipeline Task Assignment Problem; 11.2 The Greedypipe Algorithm; 11.3 Pipeline Design with Greedypipe; 11.4 A Network Processor Problem; 11.5 Conclusions; Acknowledgments; References; Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs; 12.1 Related Work; 12.2 Modeling Packet-Processing Systems; 12.3 Scheduling; 12.4 Mapping the Application to the System; 12.5 Estimating the Resource Consumption; 12.6 A Design Space Exploration Example; 12.7 Conclusions Acknowledgments |
| Record Nr. | UNINA-9910784548603321 |
| San Francisco, : Morgan Kaufmann, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Network processor design. Vol. 3, Issues and practices [electronic resource] / edited by Mark A. Franklin ... [et al.].
| Network processor design. Vol. 3, Issues and practices [electronic resource] / edited by Mark A. Franklin ... [et al.]. |
| Pubbl/distr/stampa | San Francisco, Calif. : Morgan Kaufmann, 2005 |
| Descrizione fisica | 300 p. |
| Disciplina | 621.395 |
| Altri autori (Persone) | Franklin, Mark A., 1940- |
| Soggetto topico |
Network processors - Design
Application-specific integrated circuits - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
9780120884766
0120884763 |
| Formato | Risorse elettroniche  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1. Network Processors: New Horizons -- Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk -- 2. Supporting Mixed Real-Time Workloads in -- Multithreaded Processors with Segmented -- Instruction Caches -- Patrick Crowley -- 3. Efficient Packet Classification with Digest Caches -- Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li -- 4 Towards a Flexible Network Processor Interface for -- RapidIO, Hypertransport, and PCI-Express -- Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez -- 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet -- Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar -- 6. A Hardware Platform for Network Intrusion Detection and Prevention -- Chris Clark,Wenke Lee, David Schimmel, Didier Contis, Mohamed Koň, Ashley Thomas -- 7. Packet Processing on a SIMD Stream Processor -- Jathin S. Rai, Yu-Kuen Lai, Gregory T. Byrd -- 8. A Programming Environment for Packet-Processing -- Systems: Design Considerations -- Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson,Roy Ju, Aaron Kunze, Ruiqi Lian -- 9. RNOSA Middleware Platform for Low-Cost -- Packet-Processing Devices -- Jonas Greutert, Lothar Thiele -- 10. On the Feasibility of Using Network Processors for DNA Queries -- Herbert Bos, Kaiming Huang -- 11. Pipeline Task Scheduling on Network Processors -- Mark A. Franklin, Seema Datar -- 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs -- Matthias Grünewald, J̲rg-Christian Niemann, Mario Porrmann, Ulrich Rückert -- 13. Application Analysis and Resource Mapping -- for Heterogeneous Network Processor Architectures -- Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf -- References -- Index. |
| Altri titoli varianti | Issues and practices |
| Record Nr. | UNISALENTO-991003243459707536 |
| San Francisco, Calif. : Morgan Kaufmann, 2005 | ||
| Risorse elettroniche | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
Network processor design. Vol. 2, Issues and practices [electronic resource] / edited by Mark A. Franklin ... [et al.].
| Network processor design. Vol. 2, Issues and practices [electronic resource] / edited by Mark A. Franklin ... [et al.]. |
| Pubbl/distr/stampa | San Diego, Calif. ; London : Academic, 2003 |
| Descrizione fisica | 384 p. |
| Disciplina | 621.395 |
| Altri autori (Persone) | Franklin, Mark A., 1940- |
| Soggetto topico |
Network processors - Design
Application specific integrated circuits - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
9780121981570
0121981576 |
| Formato | Risorse elettroniche |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Network Processor Design: Issues and Practics, Volume 2 -- Contents -- Preface -- Chapter 1. Network Processors: Themes and Challenges, Patrick Crowley, Mark Franklin, Haldun Hadimioglu, and Peter Z. Onufryk -- Part 1. Design Principles -- Chapter 2. A Programmable Scalable Platform for Next Generation Networking, Christos J.Georgiou, Valentina Salapura, and Monty Denneau -- Chapter 3. Power Considerations in Network Processor Design, Mark A. Franklin and Tilman Wolf -- Chapter 4. Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors, Patrick Crowley and Jean-Loup Baer -- Chapter 5. Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas, Anand Srinivasan, Philip Holman, James Anderson, Sanjoy Baruah and Jasleen Kaur -- Chapter 6. A Massively Multithreaded Packet Processor, Steve Melvin, Mario Nemirovsky, Enric Musoll, Jeff Huynh, Rodolfo Milito, Hector Urdaneta, and Koroush Saraf -- Chapter 7. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Matthias Gries, Chidamber Kulkarni, Christian Sauer and Kurt Keutzer -- Chapter 8. Packet Classification and Termination in a Protocol Processor, Ulf Nordqvist and Dake Liu -- Chapter 9. NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker and Kurt Keutzer -- Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors, Gokhan Memik and William H. Mangione-Smith -- Chapter 11. Efficient and Faithful Performance Modeling for Network-Processor Based System Designs, Prashant Pradhan, Wen Xu, Indira Nair and Sambit Sahu -- Chapter 12. High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200, Roshan K. Thomas, Brian Mark, Tommy Johnson and James Croall -- Chapter 13. Directions in Packet Classification for Network Processors, Michael E. Kounavis, Alok Kumar, Harrick Vin, Raj Yavatkar and Andrew T. Campbell -- Part 2. Practices -- Chapter 14. Implementing High-performance, High-value Traffic Management Using Agere Network Processor Solutions, Jian-Guo Chen, David Sonnier, Robert Munoz, Vinoj Kumar, and Ambalavanar Arulambalam -- Chapter 15. AMCC - nPcoreTM "NISC" Architecture, Robin Melnick and Keith Morris -- Chapter 16. Adaptable Badwidth Allocation for QoS Support in Network Processors, Clark Jeffries, Mohammad Peyravian, and Ravi Sabhikhi -- Chapter 17. IDT - Network Search Engine with QDRTM LA-1 Interface, Michael J. Miller -- Chapter 18. Implementing Voice over AAL2 on a Network Processor, Jaroslaw Sydir, Prashant Chandra, Alok Kumar, Sridhar Lakshmanamurthy, Longsong Lin, Muthaiah Venkatachalam -- Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor, Pranav Gambhire -- Chapter 20. A C-based Programming Language for Multiprocessor Network SoC Architectures. Kevin Crozier. |
| Record Nr. | UNISALENTO-991003243699707536 |
| San Diego, Calif. ; London : Academic, 2003 | ||
| Risorse elettroniche | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
