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2008 Symposium on Application specific Processors : Anaheim, CA, 8-9 June 2008
| 2008 Symposium on Application specific Processors : Anaheim, CA, 8-9 June 2008 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2008 |
| Soggetto topico |
Application-specific integrated circuits
Microprocessors Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-5090-7439-2
1-4244-2334-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204968903316 |
| [Place of publication not identified], : IEEE, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2008 Symposium on Application specific Processors : Anaheim, CA, 8-9 June 2008
| 2008 Symposium on Application specific Processors : Anaheim, CA, 8-9 June 2008 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2008 |
| Soggetto topico |
Application-specific integrated circuits
Microprocessors Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
9781509074396
1509074392 9781424423347 1424423341 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145375003321 |
| [Place of publication not identified], : IEEE, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2009 IEEE 7th Symposium on Application Specific Processors
| 2009 IEEE 7th Symposium on Application Specific Processors |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2009 |
| Descrizione fisica | 1 online resource (121 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Application-specific integrated circuits
Microprocessors |
| ISBN |
9781509068647
1509068643 9781424449385 1424449383 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910140042703321 |
| [Place of publication not identified], : IEEE, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2010 IEEE 8th Symposium on Application Specific Processors
| 2010 IEEE 8th Symposium on Application Specific Processors |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2010 |
| Descrizione fisica | 1 online resource : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico |
Application-specific integrated circuits
Microprocessors |
| ISBN |
9781424479542
1424479541 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910140696603321 |
| [Place of publication not identified], : IEEE, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2011 12th International Workshop on Microprocessor Test and Verification
| 2011 12th International Workshop on Microprocessor Test and Verification |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2011 |
| Descrizione fisica | 1 online resource |
| Disciplina | 004.16 |
| Soggetto topico | Microprocessors |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910141336503321 |
| [Place of publication not identified], : IEEE, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV) / / Institute of Electrical and Electronics Engineers
| 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV) / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 2019 |
| Descrizione fisica | 1 online resource (192 pages) |
| Disciplina | 001.6404 |
| Soggetto topico | Microprocessors |
| ISBN | 1-7281-5025-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification |
| Record Nr. | UNINA-9910389526003321 |
| Piscataway, NJ : , : IEEE, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV) / / Institute of Electrical and Electronics Engineers
| 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV) / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 2019 |
| Descrizione fisica | 1 online resource (192 pages) |
| Disciplina | 001.6404 |
| Soggetto topico | Microprocessors |
| ISBN | 1-7281-5025-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification |
| Record Nr. | UNISA-996574764303316 |
| Piscataway, NJ : , : IEEE, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2020 IEEE Hot Chips 32 Symposium (HCS) / / IEEE Hot Chips Symposium, Institute of Electrical and Electronics Engineers
| 2020 IEEE Hot Chips 32 Symposium (HCS) / / IEEE Hot Chips Symposium, Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | [Piscataway, New Jersey] : , : IEEE, , 2020 |
| Descrizione fisica | 1 online resource (various pagings) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico |
Microprocessors
Integrated circuits |
| ISBN | 1-7281-7129-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 2020 IEEE Hot Chips 32 Symposium |
| Record Nr. | UNINA-9910437218603321 |
| [Piscataway, New Jersey] : , : IEEE, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2020 IEEE Hot Chips 32 Symposium (HCS) / / IEEE Hot Chips Symposium, Institute of Electrical and Electronics Engineers
| 2020 IEEE Hot Chips 32 Symposium (HCS) / / IEEE Hot Chips Symposium, Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | [Piscataway, New Jersey] : , : IEEE, , 2020 |
| Descrizione fisica | 1 online resource (various pagings) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico |
Microprocessors
Integrated circuits |
| ISBN | 1-7281-7129-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | 2020 IEEE Hot Chips 32 Symposium |
| Record Nr. | UNISA-996575503703316 |
| [Piscataway, New Jersey] : , : IEEE, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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3D Interconnect Architectures for Heterogeneous Technologies : Modeling and Optimization / / by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck
| 3D Interconnect Architectures for Heterogeneous Technologies : Modeling and Optimization / / by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck |
| Autore | Bamberg Lennart |
| Edizione | [1st ed. 2022.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022 |
| Descrizione fisica | 1 online resource (403 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Processor Architectures |
| ISBN | 3-030-98229-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I Introduction -- 1 Introduction to 3D Technologies -- 1.1 Motivation for Heterogenous 3D ICs -- 1.2 3D Technologies -- 1.3 TSV Capacitances—A Problem Resistant to Scaling -- 1.4 Conclusion -- 2 Interconnect Architectures for 3D Technologies -- 2.1 Interconnect Architectures -- 2.2 Overview of Interconnect Architectures for 3D ICs -- 2.3 Three-dimensional Networks on chips -- 2.4 Conclusion -- Part II 3D Technology Modeling -- 3 Power and Performance Formulas -- 3.1 High-Level Formula for the Power Consumption -- 3.2 High-Level Formula for the Propagation Delay -- 3.3 Matrix Formulations -- 3.4 Evaluation -- 3.5 Conclusion -- 4 Capacitance Estimation -- 4.1 Existing Capacitance Models -- 4.2 Edge and MOS Effects on the TSV Capacitances -- 4.3 TSV Capacitance Model -- 4.4 Evaluation -- 4.5 Conclusion -- Part III System Modeling -- xiii -- xiv Contents -- 5 Application and Simulation Models -- 5.1 Overview of the Modeling Approach -- 5.2 Application Traffic Model -- 5.3 Simulation Model of 3D NoCs -- 5.4 Simulator Interfaces -- 5.5 Conclusion -- 6 Bit-level Statistics -- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for -- Single Data Streams -- 6.2 Data-Stream Multiplexing -- 6.3 Bit-Level Statistics with Data-Stream Multiplexing -- 6.4 Evaluation -- 6.5 Conclusion -- 7 Ratatoskr Framework -- 7.1 Ratatoskr for Practitioners -- 7.2 Implementation -- 7.3 Evaluation -- 7.4 Case Study: Link Power Estimation and Optimization -- 7.5 Conclusion -- Part IV 3D-Interconnect Optimization -- 8 Low-Power Technique for 3D Interconnects -- 8.1 Fundamental Idea -- 8.2 Power-Optimal TSV assignment -- 8.3 Systematic Net-to-TSV Assignments -- 8.4 Combination with Traditional Low-Power Codes -- 8.5 Evaluation -- 8.6 Conclusion -- 9 Low-Power Technique for High-Performance 3D -- Interconnects. -- 9.1 Edge-Effect-Aware Crosstalk Classification -- 9.2 Existing Approaches and Their Limitations -- 9.3 Proposed Technique -- 9.4 Extension to a Low-Power3D CAC -- 9.5 Evaluation -- 9.6 Conclusion -- 10 Low-Power Technique for High-Performance 3D -- Interconnects (Misaligned) -- 10.1 Temporal-Misalignment Effect on the Crosstalk -- 10.2 Exploiting Misalignment to Improve the Performance -- 10.3 Effect on the TSV Power Consumption -- Contents xv -- 10.4 Evaluation -- 10.5 Conclusion -- 11 Low-Power Technique for Yield-Enhanced 3D Interconnects -- 11.1 Existing TSV Yield-Enhancement Techniques -- 11.2 Preliminaries—Logical Impact of TSV Faults -- 11.3 Fundamental Idea -- 11.4 Formal Problem Description -- 11.5 TSV Redundancy Schemes -- 11.6 Evaluation -- 11.7 Case Study -- 11.8 Conclusion -- Part V NoC Optimization for Heterogeneous 3D Integration -- 12 Heterogeneous Buffering for 3D NoCs251 -- 12.1 Buffer Distributions and Depths -- 12.2 Routers with Optimized Buffer Distribution -- 12.3 Routers with Optimized Buffer Depths -- 12.4 Evaluation -- 12.5 Discussion -- 12.6 Conclusion -- 13 Heterogeneous Routing for 3D NoCs -- 13.1 Heterogeneity and Routing -- 13.2 Modeling Heterogeneous Technologies -- 13.3 Modeling Communication -- 13.4 Routing Limitations from Heterogeneity -- 13.5 Heterogeneous Routing Algorithms -- 13.6 Heterogeneous Router Architectures -- 13.7 Low-Power Routing in Heterogeneous 3D ICs -- 13.8 Evaluation -- 13.9 Discussion -- 13.10Conclusion -- 14 Heterogeneous Virtualisation for 3D NoCs -- 14.1 Problem Description -- 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance -- 14.3 Evaluation -- 14.4 Conclusion -- 15 Network Synthesis and SoC Floor Planning -- 15.1 Fundamental Idea -- 15.2 Modelling and Optimization -- 15.3 Mixed-Integer Linear Program -- 15.4 Heuristic Solution -- xvi Contents -- 15.5 Evaluation -- 15.6 Conclusion -- Part VI Finale -- 16 Conclusion -- 16.1 Putting it all together -- 16.2 Impact on Future Work -- A Appendix -- B Pseudo Codes -- C Method to Calculate the Depletion-Region Widths -- D Modeling Logical OR Relations. |
| Record Nr. | UNINA-9910735388803321 |
Bamberg Lennart
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Soggetto topico
-
Microprocessors
(836)
- Processor Architectures (708)
- Computer architecture (338)
- Electronic circuits (257)
- Computer System Implementation (180)